Lines Matching +full:divider +full:- +full:shift
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
68 .clk_def.full_dd.tbg_mux.shift = _tbg_mux_shift, \
89 .clk_def.full_dd.clk_mux.shift = _clk_mux_shift, \
94 .clk_def.full_dd.gate.shift = _gate_shift, \
110 .clk_def.full_d.tbg_mux.shift = _tbg_mux_shift, \
123 .clk_def.full_d.clk_mux.shift = _clk_mux_shift, \
128 .clk_def.full_d.gate.shift = _gate_shift, \
143 .clk_def.cpu.tbg_mux.shift = _tbg_mux_shift, \
156 .clk_def.cpu.clk_mux.shift = _clk_mux_shift, \
170 .clk_def.gate.gate.shift = _gate_shift, \
186 .clk_def.mdd.tbg_mux.shift = _tbg_mux_shift, \
207 .clk_def.mdd.clk_mux.shift = _clk_mux_shift, \
221 .clk_def.mux_gate.mux.shift = _mux_shift, \
226 .clk_def.mux_gate.gate.shift = _gate_shift, \
242 .clk_def.mux_gate_fixed.mux.shift = _mux_shift, \
247 .clk_def.mux_gate_fixed.gate.shift = _gate_shift, \
264 .clk_def.fixed.mux.shift = _mux_shift, \
269 .clk_def.fixed.gate.shift = _gate_shift, \
343 /* Double divider clock */
345 /* Single divider clock */
353 /* Clock with fixed frequency divider */
355 /* Clock with double divider, without gate */