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/linux/drivers/clk/bcm/
H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
48 /* Divider and scaling helpers */
50 /* Convert a divider into the scaled divisor value it represents. */
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
56 /* The scaled minimum divisor representable by a divider */
61 return (u64)div->u.fixed; in scaled_div_min()
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H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
27 pr_err("%s: bad policy enable offset for %s " in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
33 pr_err("%s: bad policy control offset for %s " in ccu_data_offsets_valid()
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H A Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
99 * Determine the mdiv (post divider) based on the frequency ID being used.
101 * - 25 MHz Crystal
102 * - System clock
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/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
88 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
112 #define div_mask(width) ((1 << (width)) - 1)
114 /* Extract divider instance from clock hardware instance */
125 * struct clk_wzrd - Clock wizard private data structure
148 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
150 * @hw: handle between common and hardware-specific interfaces
151 * @base: base address of register containing the divider
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H A Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
11 #include <linux/clk-provider.h>
17 #include <linux/mfd/syscon/xlnx-vcu.h>
23 #include <dt-bindings/clock/xlnx-vcu.h>
51 * struct xvcu_device - Xilinx VCU init device structure
59 * @pll_post: handle for the VCU PLL post divider
84 * struct xvcu_pll_cfg - Helper data
85 * @fbdiv: The integer portion of the feedback divider to the PLL
206 * xvcu_read - Read from the VCU register space
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
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H A Dclk-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 const struct clk_ops *mux_ops = periph->mux_ops; in clk_periph_get_parent()
18 struct clk_hw *mux_hw = &periph->mux.hw; in clk_periph_get_parent()
22 return mux_ops->get_parent(mux_hw); in clk_periph_get_parent()
28 const struct clk_ops *mux_ops = periph->mux_ops; in clk_periph_set_parent()
29 struct clk_hw *mux_hw = &periph->mux.hw; in clk_periph_set_parent()
33 return mux_ops->set_parent(mux_hw, index); in clk_periph_set_parent()
40 const struct clk_ops *div_ops = periph->div_ops; in clk_periph_recalc_rate()
41 struct clk_hw *div_hw = &periph->divider.hw; in clk_periph_recalc_rate()
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/linux/drivers/clk/stm32/
H A Dclk-stm32-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
17 #include "clk-stm32-core.h"
18 #include "reset-stm32.h"
26 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
27 struct clk_hw_onecell_data *clk_data = data->hw_clks; in stm32_rcc_clock_init()
31 max_binding = data->maxbinding; in stm32_rcc_clock_init()
35 return -ENOMEM; in stm32_rcc_clock_init()
37 clk_data->num = max_binding; in stm32_rcc_clock_init()
39 hws = clk_data->hws; in stm32_rcc_clock_init()
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/linux/drivers/clk/meson/
H A Dclk-regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
15 * struct clk_regmap - regmap backed clock
17 * @hw: handle between common and hardware-specific interfaces
39 * struct clk_regmap_gate_data - regmap backed gate specific data
41 * @offset: offset of the register controlling gate
43 * @flags: hardware-specific flags
49 unsigned int offset; member
57 return (struct clk_regmap_gate_data *)clk->data; in clk_get_regmap_gate_data()
64 * struct clk_regmap_div_data - regmap backed adjustable divider specific data
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/linux/drivers/clk/
H A Dclk-milbeaut.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
20 #define M10V_PLL1DIV2 "pll1-2"
22 #define M10V_PLL2DIV2 "pll2-2"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
31 #define M10V_PLL10DIV2 "pll10-2"
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H A Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
14 #include <linux/clk-provider.h>
64 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
82 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
84 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
85 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
114 pllclk->version); in xgene_clk_pll_recalc_rate()
136 return ERR_PTR(-ENOMEM); in xgene_register_clk_pll()
144 apmclk->version = version; in xgene_register_clk_pll()
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/linux/drivers/clk/sprd/
H A Ddiv.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Spreadtrum divider clock driver
14 * struct sprd_div_internal - Internal divider description
15 * @shift: Bit offset of the divider in its register
16 * @width: Width of the divider field in its register
18 * That structure represents a single divider, and is meant to be
23 s32 offset; member
30 .offset = _offset, \
/linux/drivers/clk/mvebu/
H A Dclk-corediv.c1 // SPDX-License-Identifier: GPL-2.0
3 * MVEBU Core divider clock
7 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
12 #include <linux/clk-provider.h>
22 * This structure describes the hardware details (bit offset and mask)
23 * to configure one particular core divider clock. Those hardware
30 unsigned int offset; member
36 * divider clocks on a given SoC. Amongst others, it points to the
37 * array of core divider clock descriptors for this SoC, as well as
50 * This structure represents one core divider clock for the clock
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/linux/drivers/clk/renesas/
H A Drzv2h-cpg.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on rzg2l-cpg.c
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "rzv2h-cpg.h"
46 #define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
69 * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
78 * @num_resets: Number of Module Resets in info->resets[]
114 * struct mod_clock - Module clock
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/linux/drivers/clk/samsung/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * blocks which includes mux and divider blocks. There are a number of other
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
48 * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
49 * @mux_sel: offset of CPU MUX_SEL register (for selecting MUX clock parent)
50 * @mux_stat: offset of CPU MUX_STAT register (for checking MUX clock status)
51 * @div_cpu0: offset of CPU DIV0 register (for modifying divider values)
52 * @div_cpu1: offset of CPU DIV1 register (for modifying divider values)
53 * @div_stat_cpu0: offset of CPU DIV0_STAT register (for checking DIV status)
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/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
82 * struct clk_alpha_pll - phase locked loop (PLL)
83 * @offset: base address of registers
92 u32 offset; member
108 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
109 * @offset: base address of registers
111 * @width: width of post-divider
112 * @post_div_shift: shift to differentiate between odd & even post-divider
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H A Dclk-regmap-mux-div.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * struct mux_div_clk - combined mux/divider clock
15 * @reg_offset: offset of the mux/divider register
16 * @hid_width: number of bits in half integer divider
20 * @div: the divider raw configuration value
23 * @clkr: handle between common and hardware-specific interfaces
/linux/drivers/clk/at91/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
58 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
61 pll->characteristics; in clk_pll_prepare()
62 u8 id = pll->id; in clk_pll_prepare()
64 int offset = PLL_REG(id); in clk_pll_prepare() local
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/linux/drivers/clk/sunxi-ng/
H A Dccu_div.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
15 * struct ccu_div_internal - Internal divider description
16 * @shift: Bit offset of the divider in its register
17 * @width: Width of the divider field in its register
18 * @max: Maximum value allowed for that divider. This is the
21 * @flags: clk_divider flags to apply on this divider
22 * @table: Divider table pointer (if applicable)
24 * That structure represents a single divider, and is meant to be
36 u32 offset; member
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/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
23 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) in aty_ld_pll_ct() argument
27 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par); in aty_ld_pll_ct()
32 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) in aty_st_pll_ct() argument
35 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); in aty_st_pll_ct()
38 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); in aty_st_pll_ct()
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
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/linux/drivers/mfd/
H A Dsm501.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/platform_data/i2c-gpio.h>
25 #include <linux/sm501-regs.h>
135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); in sm501_dump_clk()
136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); in sm501_dump_clk()
137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); in sm501_dump_clk()
138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); in sm501_dump_clk()
163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", in sm501_dump_clk()
166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", in sm501_dump_clk()
169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); in sm501_dump_clk()
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_a.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
31 #define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
52 #define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
56 #define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
57 #define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
65 #define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset)) argument
98 u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
100 u16 offset, u16 value);
101 u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
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/linux/Documentation/devicetree/bindings/clock/
H A Darm,syscon-icst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
19 an ICST clock request after a write to the 32 bit register at an offset
22 writing a special token to another offset in the system controller.
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
28 the value on the pins, not the resulting output divider).
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/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
19 #include "clk-sg2042.h"
23 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
24 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
25 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
26 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
27 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
28 #define R_DPLL1_CONTROL (0xFC - R_PLL_BEGIN)
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