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/linux/drivers/clk/bcm/
H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
48 /* Divider and scaling helpers */
50 /* Convert a divider into the scaled divisor value it represents. */
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
56 /* The scaled minimum divisor representable by a divider */
61 return (u64)div->u.fixed; in scaled_div_min()
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H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
27 pr_err("%s: bad policy enable offset for %s " in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
33 pr_err("%s: bad policy control offset for %s " in ccu_data_offsets_valid()
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H A Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
99 * Determine the mdiv (post divider) based on the frequency ID being used.
101 * - 25 MHz Crystal
102 * - System clock
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/linux/drivers/clk/stm32/
H A Dclk-stm32-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
17 #include "clk-stm32-core.h"
18 #include "reset-stm32.h"
26 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
27 struct clk_hw_onecell_data *clk_data = data->hw_clks; in stm32_rcc_clock_init()
31 max_binding = data->maxbinding; in stm32_rcc_clock_init()
35 return -ENOMEM; in stm32_rcc_clock_init()
37 clk_data->num = max_binding; in stm32_rcc_clock_init()
39 hws = clk_data->hws; in stm32_rcc_clock_init()
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/linux/drivers/clk/
H A Dclk-milbeaut.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
20 #define M10V_PLL1DIV2 "pll1-2"
22 #define M10V_PLL2DIV2 "pll2-2"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
31 #define M10V_PLL10DIV2 "pll10-2"
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/linux/drivers/clk/sprd/
H A Ddiv.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Spreadtrum divider clock driver
14 * struct sprd_div_internal - Internal divider description
15 * @shift: Bit offset of the divider in its register
16 * @width: Width of the divider field in its register
18 * That structure represents a single divider, and is meant to be
23 s32 offset; member
30 .offset = _offset, \
/linux/drivers/clk/mvebu/
H A Dclk-corediv.c1 // SPDX-License-Identifier: GPL-2.0
3 * MVEBU Core divider clock
7 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
12 #include <linux/clk-provider.h>
22 * This structure describes the hardware details (bit offset and mask)
23 * to configure one particular core divider clock. Those hardware
30 unsigned int offset; member
36 * divider clocks on a given SoC. Amongst others, it points to the
37 * array of core divider clock descriptors for this SoC, as well as
50 * This structure represents one core divider clock for the clock
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/linux/Documentation/devicetree/bindings/mfd/
H A Dgateworks-gsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Watchdog Timer
15 - GPIO
16 - Pushbutton controller
17 - Hardware monitor with ADC's for temperature and voltage rails and
21 - Tim Harvey <tharvey@gateworks.com>
25 pattern: "gsc@[0-9a-f]{1,2}"
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/linux/drivers/clk/at91/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
58 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
61 pll->characteristics; in clk_pll_prepare()
62 u8 id = pll->id; in clk_pll_prepare()
64 int offset = PLL_REG(id); in clk_pll_prepare() local
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/linux/drivers/clk/sunxi-ng/
H A Dccu_div.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
15 * struct ccu_div_internal - Internal divider description
16 * @shift: Bit offset of the divider in its register
17 * @width: Width of the divider field in its register
18 * @max: Maximum value allowed for that divider. This is the
21 * @flags: clk_divider flags to apply on this divider
22 * @table: Divider table pointer (if applicable)
24 * That structure represents a single divider, and is meant to be
36 u32 offset; member
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/linux/drivers/video/fbdev/aty/
H A Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
23 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par) in aty_ld_pll_ct() argument
27 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par); in aty_ld_pll_ct()
32 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par) in aty_st_pll_ct() argument
35 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par); in aty_st_pll_ct()
38 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par); in aty_st_pll_ct()
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
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H A Dmach64_gx.c1 // SPDX-License-Identifier: GPL-2.0
36 #define MAX_N 255-8
60 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); in aty_StrobeClock()
69 static void aty_st_514(int offset, u8 val, const struct atyfb_par *par) in aty_st_514() argument
73 aty_st_8(DAC_W_INDEX, offset & 0xff, par); in aty_st_514()
75 aty_st_8(DAC_DATA, (offset >> 8) & 0xff, par); in aty_st_514()
83 struct atyfb_par *par = (struct atyfb_par *) info->par; in aty_set_dac_514()
154 pll->ibm514.m = RGB514_clocks[i].m; in aty_var_to_pll_514()
155 pll->ibm514.n = RGB514_clocks[i].n; in aty_var_to_pll_514()
158 return -EINVAL; in aty_var_to_pll_514()
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/linux/drivers/mfd/
H A Dsm501.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/platform_data/i2c-gpio.h>
25 #include <linux/sm501-regs.h>
135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); in sm501_dump_clk()
136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); in sm501_dump_clk()
137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); in sm501_dump_clk()
138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); in sm501_dump_clk()
163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", in sm501_dump_clk()
166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", in sm501_dump_clk()
169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); in sm501_dump_clk()
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/linux/drivers/clk/qcom/
H A Dclk-regmap-mux-div.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk-provider.h>
11 #include "clk-regmap.h"
14 * struct mux_div_clk - combined mux/divider clock
15 * @reg_offset: offset of the mux/divider register
16 * @hid_width: number of bits in half integer divider
20 * @div: the divider raw configuration value
23 * @clkr: handle between common and hardware-specific interfaces
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_a.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
31 #define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
52 #define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
56 #define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
57 #define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
65 #define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset)) argument
98 u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
100 u16 offset, u16 value);
101 u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
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/linux/drivers/iio/adc/
H A Dcpcap-adc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2009-2010 Motorola, Inc.
27 #include <linux/mfd/motorola-cpcap.h>
86 * struct cpcap_adc_ato - timing settings for cpcap adc
103 * struct cpcap_adc - cpcap adc device driver data
125 * enum cpcap_adc_channel - cpcap adc channels
156 * enum cpcap_adc_timing - cpcap adc timing options
168 * struct cpcap_adc_phasing_tbl - cpcap phasing table
169 * @offset: offset in the phasing table
171 * @divider: divider in the phasing table
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/linux/Documentation/devicetree/bindings/clock/
H A Darm,syscon-icst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
19 an ICST clock request after a write to the 32 bit register at an offset
22 writing a special token to another offset in the system controller.
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
26 different values and sometimes also hard-wires the output divider. They
28 the value on the pins, not the resulting output divider).
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/linux/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_display.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
52 struct drm_device *dev = crtc->dev; in avivo_crtc_load_lut()
53 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_load_lut()
57 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
60 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
61 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
62 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
64 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
65 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
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/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
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/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
14 driver Copyright(c) 2003 - 2004 Intel Corporation.
49 /* OFDM (A) registers of a G-PHY */
51 /* Extended G-PHY registers */
55 /* Extended G-PHY Registers */
57 #define B43legacy_PHY_GTABCTL B43legacy_PHY_EXTG(0x03) /* G-PHY table control (see below) */
58 #define B43legacy_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
59 #define B43legacy_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
61 #define B43legacy_PHY_GTABDATA B43legacy_PHY_EXTG(0x04) /* G-PHY table data */
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-at91.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Parallel I/O Controller (PIO) - System peripherals registers.
29 #define PIO_MDER 0x50 /* Multi-driver Enable Register */
30 #define PIO_MDDR 0x54 /* Multi-driver Disable Register */
31 #define PIO_MDSR 0x58 /* Multi-driver Status Register */
32 #define PIO_PUDR 0x60 /* Pull-up Disable Register */
33 #define PIO_PUER 0x64 /* Pull-up Enable Register */
34 #define PIO_PUSR 0x68 /* Pull-up Status Register */
43 #define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
44 #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
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/linux/drivers/hwmon/
H A Dmlxreg-fan.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
28 * The logic in a programmable device measures the time t-high by sampling the
29 * tachometer every t-sample (with the default value 11.32 uS) and increment
31 * RPM = 15 / (t-sample * (K + Regval)), where:
33 * - 0xff - represents tachometer fault;
34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
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/linux/drivers/clk/microchip/
H A Dclk-mpfs-ccc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/microchip,mpfs-clock.h>
14 /* address offset of control registers */
76 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; in mpfs_ccc_pll_recalc_rate()
77 void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; in mpfs_ccc_pll_recalc_rate()
91 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; in mpfs_ccc_pll_get_parent()
118 struct clk_divider divider; member
126 .divider.shift = _shift, \
127 .divider.width = _width, \
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