Lines Matching +full:divider +full:- +full:offset

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
99 * Determine the mdiv (post divider) based on the frequency ID being used.
101 * - 25 MHz Crystal
102 * - System clock
103 * - PLL channel 0 (slow clock)
104 * - PLL channel 1 (fast clock)
121 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in __get_mdiv()
128 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); in __get_mdiv()
135 mdiv = -EFAULT; in __get_mdiv()
146 val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET); in __get_ndiv()
149 * offset mode is active. Read the ndiv from the PLLARM OFFSET in __get_ndiv()
159 /* offset mode not active */ in __get_ndiv()
160 val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); in __get_ndiv()
166 val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET); in __get_ndiv()
177 * divider values:
178 * pdiv = ARM PLL pre-divider
180 * mdiv = ARM PLL post divider
195 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in iproc_arm_pll_recalc_rate()
197 pll->rate = parent_rate; in iproc_arm_pll_recalc_rate()
198 return pll->rate; in iproc_arm_pll_recalc_rate()
202 val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET); in iproc_arm_pll_recalc_rate()
204 pll->rate = 0; in iproc_arm_pll_recalc_rate()
216 pll->rate = 0; in iproc_arm_pll_recalc_rate()
219 pll->rate = (ndiv * parent_rate) >> 20; in iproc_arm_pll_recalc_rate()
220 pll->rate = (pll->rate / pdiv) / mdiv; in iproc_arm_pll_recalc_rate()
223 pll->rate, parent_rate); in iproc_arm_pll_recalc_rate()
227 return pll->rate; in iproc_arm_pll_recalc_rate()
245 pll->base = of_iomap(node, 0); in iproc_armpll_setup()
246 if (WARN_ON(!pll->base)) in iproc_armpll_setup()
249 init.name = node->name; in iproc_armpll_setup()
255 pll->hw.init = &init; in iproc_armpll_setup()
257 ret = clk_hw_register(NULL, &pll->hw); in iproc_armpll_setup()
261 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw); in iproc_armpll_setup()
268 clk_hw_unregister(&pll->hw); in iproc_armpll_setup()
270 iounmap(pll->base); in iproc_armpll_setup()