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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
14 reg = <0x0040>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
21 reg = <0x0108>;
[all …]
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
14 reg = <0x0040>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
18 reg = <0x0d40>;
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 reg = <0xa00>;
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
16 reg = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
[all …]
H A Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
7 reg = <0x400 0x40>;
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
23 reg = <0x440 0x30>;
25 clock-indices = <1>, <2>, <3>, <4>;
[all …]
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
13 reg = <0x4>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
H A Domap3430es1-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,wait-gate-clock";
12 reg = <0x0b10>;
13 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,divider-clock";
20 ti,max-div = <7>;
21 reg = <0x0b40>;
22 ti,index-starts-at-one;
[all …]
H A Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
12 reg = <0x40 0x40>;
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
24 reg = <0x80 0x30>;
26 clock-names = "clkinp", "clkinpulow";
[all …]
H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
18 reg = <0xa14>;
19 #clock-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 aes1_ick: clock-aes1-ick@3 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
17 reg = <0x02310108 4>;
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_composite.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
79 if (sc->grf) in rk_clk_composite_read_4()
80 *val = SYSCON_READ_4(sc->grf, addr); in rk_clk_composite_read_4()
91 if (sc->grf) in rk_clk_composite_write_4()
92 SYSCON_WRITE_4(sc->grf, addr, val | (0xffff << 16)); in rk_clk_composite_write_4()
123 if ((sc->flags & RK_CLK_COMPOSITE_GRF) != 0) { in rk_clk_composite_init()
124 sc->grf = rk_clk_composite_get_grf(clk); in rk_clk_composite_init()
125 if (sc->grf == NULL) in rk_clk_composite_init()
131 if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) != 0) { in rk_clk_composite_init()
[all …]
H A Drk_clk_armclk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 READ4(clk, sc->muxdiv_offset, &val); in rk_clk_armclk_init()
91 idx = (val & sc->mux_mask) >> sc->mux_shift; in rk_clk_armclk_init()
108 val |= index << sc->mux_shift; in rk_clk_armclk_set_mux()
109 val |= sc->mux_mask << RK_ARMCLK_WRITE_MASK_SHIFT; in rk_clk_armclk_set_mux()
110 dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val); in rk_clk_armclk_set_mux()
111 WRITE4(clk, sc->muxdiv_offset, val); in rk_clk_armclk_set_mux()
121 uint32_t reg, div; in rk_clk_armclk_recalc() local
127 READ4(clk, sc->muxdiv_offset, &reg); in rk_clk_armclk_recalc()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Damlogic,c3-peripherals-clkc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
4 ---
5 $id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Jerome Brunet <jbrunet@baylibre.com>
13 - Xianwei Zhao <xianwei.zhao@amlogic.com>
14 - Chuan Liu <chuan.liu@amlogic.com>
18 const: amlogic,c3-peripherals-clkc
[all …]
/freebsd/sys/dev/sdhci/
H A Dsdhci_fsl_fdt.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2020 - 2021 Alstom Group.
5 * Copyright (c) 2020 - 2021 Semihalf.
56 #define RD4 (sc->read)
57 #define WR4 (sc->write)
219 .syscon_compat = "fsl,ls1012a-scfg",
234 .syscon_compat = "fsl,ls1046a-scfg",
250 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data},
251 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data},
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
61 - $ref: ti,autoidle.yaml#
[all …]
/freebsd/sys/arm/ti/
H A Dti_spi.c1 /*-
78 int clk, conf, ctrl, div, i, j, wl; in ti_spi_printr() local
80 uint32_t reg; in ti_spi_printr() local
83 reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG); in ti_spi_printr()
84 device_printf(dev, "SYSCONFIG: %#x\n", reg); in ti_spi_printr()
85 reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS); in ti_spi_printr()
86 device_printf(dev, "SYSSTATUS: %#x\n", reg); in ti_spi_printr()
87 reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS); in ti_spi_printr()
88 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); in ti_spi_printr()
89 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); in ti_spi_printr()
[all …]
/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_ro_div.c1 /*-
50 * This is a read-only divisor table node.
69 uint32_t reg, idx, div = 1; in qcom_clk_ro_div_recalc() local
79 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); in qcom_clk_ro_div_recalc()
80 CLKDEV_READ_4(clknode_get_device(sc->clknode), sc->offset, &reg); in qcom_clk_ro_div_recalc()
81 CLKDEV_DEVICE_UNLOCK(clknode_get_device(sc->clknode)); in qcom_clk_ro_div_recalc()
83 idx = (reg >> sc->shift) & ((1U << sc->width) - 1); in qcom_clk_ro_div_recalc()
85 for (i = 0; (sc->div_tbl[i].div != 0); i++) { in qcom_clk_ro_div_recalc()
86 if (idx == sc->div_tbl[i].val) { in qcom_clk_ro_div_recalc()
87 div = sc->div_tbl[i].div; in qcom_clk_ro_div_recalc()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
[all …]

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