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/linux/drivers/clk/bcm/
H A Dclk-iproc-asiu.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
22 struct iproc_asiu_div div; member
38 struct iproc_asiu_clk *clk = to_asiu_clk(hw); in iproc_asiu_clk_enable() local
39 struct iproc_asiu *asiu = clk->asiu; in iproc_asiu_clk_enable()
43 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
46 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
47 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
48 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
[all …]
/linux/drivers/clk/mxs/
H A Dclk-div.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
9 #include "clk.h"
12 * struct clk_div - mxs integer divider clock
38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_determine_rate() local
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
[all …]
H A Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
10 #include "clk.h"
13 * struct clk_frac - mxs fractional divider clock
37 u32 div; in clk_frac_recalc_rate() local
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
41 div &= (1 << frac->width) - 1; in clk_frac_recalc_rate()
43 tmp_rate = (u64)parent_rate * div; in clk_frac_recalc_rate()
44 return tmp_rate >> frac->width; in clk_frac_recalc_rate()
51 unsigned long parent_rate = req->best_parent_rate; in clk_frac_determine_rate()
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
[all …]
H A Dclk-sun9i-cpus.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
33 #define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ argument
34 (div << SUN9I_CPUS_DIV_SHIFT))
39 #define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ argument
40 (div << SUN9I_CPUS_PLL4_DIV_SHIFT))
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
[all …]
H A Dclk-sun8i-mbus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
28 const char *clk_name = node->name; in sun8i_a23_mbus_setup()
30 struct clk_divider *div; in sun8i_a23_mbus_setup() local
33 struct clk *clk; in sun8i_a23_mbus_setup() local
43 pr_err("Could not get registers for sun8i-mbus-clk\n"); in sun8i_a23_mbus_setup()
47 div = kzalloc(sizeof(*div), GFP_KERNEL); in sun8i_a23_mbus_setup()
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H A Dclk-sun6i-ar100.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
11 #include <linux/clk-provider.h>
17 #include "clk-factors.h"
20 * sun6i_get_ar100_factors - Calculates factors p, m for AR100
27 unsigned long div; in sun6i_get_ar100_factors() local
31 if (req->rate > req->parent_rate) in sun6i_get_ar100_factors()
32 req->rate = req->parent_rate; in sun6i_get_ar100_factors()
34 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ar100_factors()
36 if (div < 32) in sun6i_get_ar100_factors()
[all …]
H A Dclk-a10-ve.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
8 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
24 * sunxi_ve_reset... - reset bit in ve clk registers handling
42 spin_lock_irqsave(data->lock, flags); in sunxi_ve_reset_assert()
44 reg = readl(data->reg); in sunxi_ve_reset_assert()
45 writel(reg & ~BIT(SUN4I_VE_RESET), data->reg); in sunxi_ve_reset_assert()
47 spin_unlock_irqrestore(data->lock, flags); in sunxi_ve_reset_assert()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
12 #include "clk.h"
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
29 if (div < 0) in get_div()
[all …]
H A Dclk-tegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Based on drivers/clk/tegra/clk-emc.c
7 * Copyright (C) 2019 GRATE-DRIVER project
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
13 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
21 #include "clk.h"
58 u32 val, div; in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
61 div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK; in emc_recalc_rate()
[all …]
H A Dclk-sdmmc-mux.c1 // SPDX-License-Identifier: GPL-2.0
5 * based on clk-mux.c
9 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
13 #include <linux/clk-provider.h>
18 #include "clk.h"
50 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_get_parent()
73 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
82 writel(val, sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
92 int div; in clk_sdmmc_mux_recalc_rate() local
95 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_recalc_rate()
[all …]
/linux/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (req->rate / fix->mult) * fix->div; in clk_factor_determine_rate()
42 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); in clk_factor_determine_rate()
[all …]
H A Dclk-qoriq.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
34 #define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
40 struct clk *clk; member
45 struct clockgen_pll_div div[MAX_PLL_DIV]; member
54 int div; /* PLL_DIVn */ member
83 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
92 struct clk *sysclk, *coreclk;
[all …]
/linux/drivers/clk/rockchip/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * samsung/clk.c
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
26 #include "../clk-fractional-divider.h"
27 #include "clk.h"
33 * src1 --|--\
34 * |M |--[GATE]-[DIV]-
35 * src2 --|--/
[all …]
/linux/drivers/clk/spear/
H A Dclk-frac-synth.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "clk-frac-synth: " fmt
11 #include <linux/clk-provider.h>
15 #include "clk.h"
24 * Fout= Fin/2*div (division factor)
25 * div is 17 bits:-
26 * 0-13 (fractional part)
27 * 14-16 (integer part)
28 * div is (16-14 bits).(13-0 bits) (in binary)
30 * Fout = Fin/(2 * div)
[all …]
/linux/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
17 #include "clk.h"
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
29 * @table: the div table that the divider supports
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
/linux/drivers/clk/microchip/
H A Dclk-core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include <asm/mach-pic32/pic32.h>
15 #include "clk-core.h"
78 /* add instruction pipeline delay while CPU clock is in-transition. */
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
125 unsigned long div, div_up; in calc_best_divided_rate() local
131 div = parent_rate / rate; in calc_best_divided_rate()
[all …]
/linux/drivers/clk/pistachio/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
13 #include "clk.h"
24 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); in pistachio_clk_alloc_provider()
25 if (!p->clk_data.clks) in pistachio_clk_alloc_provider()
27 p->clk_data.clk_num = num_clks; in pistachio_clk_alloc_provider()
28 p->node = node; in pistachio_clk_alloc_provider()
29 p->base = of_iomap(node, 0); in pistachio_clk_alloc_provider()
30 if (!p->base) { in pistachio_clk_alloc_provider()
[all …]
/linux/drivers/pwm/
H A Dpwm-keembay.c1 // SPDX-License-Identifier: GPL-2.0
10 * - Upon disabling a channel, the currently running
17 #include <linux/clk.h>
40 struct clk *clk; member
54 static int keembay_clk_enable(struct device *dev, struct clk *clk) in keembay_clk_enable() argument
58 ret = clk_prepare_enable(clk); in keembay_clk_enable()
62 return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk); in keembay_clk_enable()
73 u32 buff = readl(priv->base + offset); in keembay_pwm_update_bits()
76 writel(buff, priv->base + offset); in keembay_pwm_update_bits()
99 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_get_state()
[all …]
H A Dpwm-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car PWM Timer driver
8 * - The hardware cannot generate a 0% duty cycle.
12 #include <linux/clk.h>
43 struct clk *clk; member
54 writel(data, rp->base + offset); in rcar_pwm_write()
59 return readl(rp->base + offset); in rcar_pwm_read()
75 unsigned long clk_rate = clk_get_rate(rp->clk); in rcar_pwm_get_clock_division()
76 u64 div, tmp; in rcar_pwm_get_clock_division() local
79 return -EINVAL; in rcar_pwm_get_clock_division()
[all …]
/linux/drivers/clk/renesas/
H A Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
38 unsigned int div; member
51 val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP)) in cpg_div6_clock_enable()
52 | CPG_DIV6_DIV(clock->div - 1); in cpg_div6_clock_enable()
[all …]
/linux/drivers/clk/ingenic/
H A Dcgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
28 to_clk_info(struct ingenic_clk *clk) in to_clk_info() argument
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
[all …]
/linux/drivers/clk/ti/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
15 #include <linux/clk/ti.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
42 if (clkt->val > max_val) in _setup_mask()
[all …]
/linux/drivers/media/platform/microchip/
H A Dmicrochip-isc-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
17 #include "microchip-isc-regs.h"
18 #include "microchip-isc.h"
23 struct regmap *regmap = isc_clk->regmap; in isc_wait_clk_stable()
35 return -ETIMEDOUT; in isc_wait_clk_stable()
43 ret = pm_runtime_resume_and_get(isc_clk->dev); in isc_clk_prepare()
56 pm_runtime_put_sync(isc_clk->dev); in isc_clk_unprepare()
62 u32 id = isc_clk->id; in isc_clk_enable()
[all …]
/linux/drivers/staging/media/deprecated/atmel/
H A Datmel-isc-clk.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
17 #include "atmel-isc-regs.h"
18 #include "atmel-isc.h"
23 struct regmap *regmap = isc_clk->regmap; in isc_wait_clk_stable()
35 return -ETIMEDOUT; in isc_wait_clk_stable()
43 ret = pm_runtime_resume_and_get(isc_clk->dev); in isc_clk_prepare()
56 pm_runtime_put_sync(isc_clk->dev); in isc_clk_unprepare()
62 u32 id = isc_clk->id; in isc_clk_enable()
[all …]

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