1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27  * struct div6_clock - CPG 6 bit divider clock
28  * @hw: handle between common and hardware-specific interfaces
29  * @reg: IO-remapped register
30  * @div: divisor value (1-64)
38 	unsigned int div;  member
51 	val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))  in cpg_div6_clock_enable()
52 	    | CPG_DIV6_DIV(clock->div - 1);  in cpg_div6_clock_enable()
53 	writel(val, clock->reg);  in cpg_div6_clock_enable()
63 	val = readl(clock->reg);  in cpg_div6_clock_disable()
66 	 * DIV6 clocks require the divisor field to be non-zero when stopping  in cpg_div6_clock_disable()
68 	 * re-enabled later if the divisor field is changed when stopping the  in cpg_div6_clock_disable()
73 	writel(val, clock->reg);  in cpg_div6_clock_disable()
80 	return !(readl(clock->reg) & CPG_DIV6_CKSTP);  in cpg_div6_clock_is_enabled()
88 	return parent_rate / clock->div;  in cpg_div6_clock_recalc_rate()
94 	unsigned int div;  in cpg_div6_clock_calc_div()  local
99 	div = DIV_ROUND_CLOSEST(parent_rate, rate);  in cpg_div6_clock_calc_div()
100 	return clamp(div, 1U, 64U);  in cpg_div6_clock_calc_div()
109 	unsigned int i, min_div, max_div, div;  in cpg_div6_clock_determine_rate()  local
121 		min_div = max(DIV_ROUND_UP(prate, req->max_rate), 1UL);  in cpg_div6_clock_determine_rate()
122 		max_div = req->min_rate ? min(prate / req->min_rate, 64UL) : 64;  in cpg_div6_clock_determine_rate()
126 		div = cpg_div6_clock_calc_div(req->rate, prate);  in cpg_div6_clock_determine_rate()
127 		div = clamp(div, min_div, max_div);  in cpg_div6_clock_determine_rate()
128 		calc_rate = prate / div;  in cpg_div6_clock_determine_rate()
129 		diff = calc_rate > req->rate ? calc_rate - req->rate  in cpg_div6_clock_determine_rate()
130 					     : req->rate - calc_rate;  in cpg_div6_clock_determine_rate()
140 		return -EINVAL;  in cpg_div6_clock_determine_rate()
142 	req->best_parent_rate = best_prate;  in cpg_div6_clock_determine_rate()
143 	req->best_parent_hw = best_parent;  in cpg_div6_clock_determine_rate()
144 	req->rate = best_rate;  in cpg_div6_clock_determine_rate()
152 	unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);  in cpg_div6_clock_set_rate()  local
155 	clock->div = div;  in cpg_div6_clock_set_rate()
157 	val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;  in cpg_div6_clock_set_rate()
160 		writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);  in cpg_div6_clock_set_rate()
171 	if (clock->src_mask == 0)  in cpg_div6_clock_get_parent()
174 	hw_index = (readl(clock->reg) & clock->src_mask) >>  in cpg_div6_clock_get_parent()
175 		   __ffs(clock->src_mask);  in cpg_div6_clock_get_parent()
177 		if (clock->parents[i] == hw_index)  in cpg_div6_clock_get_parent()
192 		return -EINVAL;  in cpg_div6_clock_set_parent()
194 	src = clock->parents[index] << __ffs(clock->src_mask);  in cpg_div6_clock_set_parent()
195 	writel((readl(clock->reg) & ~clock->src_mask) | src, clock->reg);  in cpg_div6_clock_set_parent()
221 		 * R/SH-Mobile SoCs, while the resume functionality is only  in cpg_div6_clock_notifier_call()
222 		 * needed on R-Car Gen3.  in cpg_div6_clock_notifier_call()
224 		if (__clk_get_enable_count(clock->hw.clk))  in cpg_div6_clock_notifier_call()
225 			cpg_div6_clock_enable(&clock->hw);  in cpg_div6_clock_notifier_call()
227 			cpg_div6_clock_disable(&clock->hw);  in cpg_div6_clock_notifier_call()
235  * cpg_div6_register - Register a DIV6 clock
242 struct clk * __init cpg_div6_register(const char *name,  in cpg_div6_register()
251 	struct clk *clk;  in cpg_div6_register()  local
256 		return ERR_PTR(-ENOMEM);  in cpg_div6_register()
258 	clock->reg = reg;  in cpg_div6_register()
264 	clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;  in cpg_div6_register()
269 		clock->src_mask = 0;  in cpg_div6_register()
272 		/* clock with EXSRC bits 6-7 */  in cpg_div6_register()
273 		clock->src_mask = GENMASK(7, 6);  in cpg_div6_register()
276 		/* VCLK with EXSRC bits 12-14 */  in cpg_div6_register()
277 		clock->src_mask = GENMASK(14, 12);  in cpg_div6_register()
282 		clk = ERR_PTR(-EINVAL);  in cpg_div6_register()
290 			clock->parents[valid_parents] = i;  in cpg_div6_register()
301 	clock->hw.init = &init;  in cpg_div6_register()
303 	clk = clk_register(NULL, &clock->hw);  in cpg_div6_register()
304 	if (IS_ERR(clk))  in cpg_div6_register()
308 		clock->nb.notifier_call = cpg_div6_clock_notifier_call;  in cpg_div6_register()
309 		raw_notifier_chain_register(notifiers, &clock->nb);  in cpg_div6_register()
312 	return clk;  in cpg_div6_register()
316 	return clk;  in cpg_div6_register()
323 	const char *clk_name = np->name;  in cpg_div6_clock_init()
325 	struct clk *clk;  in cpg_div6_clock_init()  local
348 	of_property_read_string(np, "clock-output-names", &clk_name);  in cpg_div6_clock_init()
353 	clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);  in cpg_div6_clock_init()
354 	if (IS_ERR(clk)) {  in cpg_div6_clock_init()
356 		       __func__, np, PTR_ERR(clk));  in cpg_div6_clock_init()
360 	of_clk_add_provider(np, of_clk_src_simple_get, clk);  in cpg_div6_clock_init()
370 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);