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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dallwinner,sun4i-a10-display-engine.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Pipeline
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
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H A Darm,malidp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/arm,malidp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP)
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
14 The following bindings apply to a family of Display Processors sold as
22 - arm,mali-dp500
23 - arm,mali-dp550
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H A Dallwinner,sun4i-a10-display-frontend.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Frontend
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine frontend does formats conversion, scaling,
20 - allwinner,sun4i-a10-display-frontend
21 - allwinner,sun5i-a13-display-frontend
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H A Dallwinner,sun8i-a83t-de2-mixer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-de2-mixer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner Display Engine 2.0 Mixer
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun8i-a83t-de2-mixer-0
17 - allwinner,sun8i-a83t-de2-mixer-1
18 - allwinner,sun8i-h3-de2-mixer-0
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H A Dallwinner,sun4i-a10-display-backend.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-backend.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Backend
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine backend exposes layers and sprites to the system.
19 - allwinner,sun4i-a10-display-backend
20 - allwinner,sun5i-a13-display-backend
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/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx8qxp-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller
10 The Freescale i.MX8qxp Display Controller(DC) is comprised of three main
11 components that include a blit engine for 2D graphics accelerations, display
12 controller for display output processing, as well as a command sequencer.
14 Display buffers Source buffers
17 +---------------------------+------------+------------------+-+-+------+
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H A Dfsl,imx8qxp-dc-display-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Display Engine
10 All Processing Units that operate in a display clock domain. Pixel pipeline
11 is driven by a video timing and cannot be stalled. Implements all display
15 - Liu Ying <victor.liu@nxp.com>
19 const: fsl,imx8qxp-dc-display-engine
24 reg-names:
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H A Dfsl,imx8qxp-dc-matrix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-matrix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Color Matrix
10 The unit supports linear color transformation, alpha pre-multiply and
14 - Liu Ying <victor.liu@nxp.com>
18 const: fsl,imx8qxp-dc-matrix
24 reg-names:
26 - const: cfg # matrix in display engine
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H A Dfsl,imx8qxp-dc-extdst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-extdst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller External Destination Interface
11 processing pipeline of the Pixel Engine, which is 30-bit RGB plus 8-bit Alpha,
12 and a Display Engine.
14 It comprises the following built-in Gamma apply function.
16 +------X-----------------------+
19 | +-------+ |
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H A Dfsl,imx8qxp-dc-blit-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Blit Engine
35 Modify colors by linear or non-linear transformations.
47 Performs a re-sampling of the source image with any pattern. The sample
59 - Liu Ying <victor.liu@nxp.com>
63 const: fsl,imx8qxp-dc-blit-engine
68 reg-names:
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H A Dfsl,imx8qxp-dc-pixel-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Pixel Engine
13 functions. Interconnection of Processing Units is re-configurable.
16 - Liu Ying <victor.liu@nxp.com>
20 const: fsl,imx8qxp-dc-pixel-engine
28 "#address-cells":
31 "#size-cells":
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H A Dfsl,imx8qxp-dc-scaling-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-scaling-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Scaling Engine
11 re-sampling with 1/32 sub pixel precision.
24 +-----------+
27 +-----------+
31 |\ +-----------+
32 ------+ | | |
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,imx8qxp-dc-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
19 Alternatively the un-masked trigger signals for all HW events are provided,
26 - Liu Ying <victor.liu@nxp.com>
30 const: fsl,imx8qxp-dc-intc
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
20 - $ref: /schemas/display/dsi-controller.yaml#
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H A Dmediatek,ethdr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
15 designed for HDR video and graphics conversion in the external display path.
18 output the required HDR or SDR signal to the subsequent display path.
19 This engine is composed of two video frontends, two graphic frontends,
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H A Dmediatek,dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The MediaTek DPI and DP_INTF function blocks are a sink of the display
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21 - enum:
22 - mediatek,mt2701-dpi
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/freebsd/crypto/openssl/doc/man1/
H A Dopenssl-engine.pod.in2 {- OpenSSL::safe::output_do_not_edit_headers(); -}
6 openssl-engine - load and query engines
10 B<openssl engine>
11 [B<-help>]
12 [B<-v>]
13 [B<-vv>]
14 [B<-vvv>]
15 [B<-vvvv>]
16 [B<-c>]
17 [B<-t>]
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H A Dopenssl-verify.pod.in2 {- OpenSSL::safe::output_do_not_edit_headers(); -}
6 openssl-verify - certificate verification command
11 [B<-help>]
12 [B<-CRLfile> I<filename>|I<uri>]
13 [B<-crl_download>]
14 [B<-show_chain>]
15 [B<-verbose>]
16 [B<-trusted> I<filename>|I<uri>]
17 [B<-untrusted> I<filename>|I<uri>]
18 [B<-vfyopt> I<nm>:I<v>]
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/freebsd/crypto/openssl/apps/
H A Dengine.c2 * Copyright 2000-2025 The OpenSSL Project Authors. All Rights Reserved.
10 /* We need to use some engine deprecated APIs */
21 #include <openssl/engine.h>
32 {OPT_HELP_STR, 1, '-', "Usage: %s [options] engine...\n"},
35 {"help", OPT_HELP, '-', "Display this summary"},
36 {"t", OPT_T, '-', "Check that specified engine is available"},
37 {"pre", OPT_PRE, 's', "Run command against the ENGINE before loading it"},
38 {"post", OPT_POST, 's', "Run command against the ENGINE after loading it"},
41 {"v", OPT_V, '-', "List 'control commands' For each specified engine"},
42 {"vv", OPT_VV, '-', "Also display each command's description"},
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/freebsd/secure/usr.bin/openssl/man/
H A Dopenssl-verify.11 .\" -*- mode: troff; coding: utf-8 -*-
57 .IX Title "OPENSSL-VERIFY 1ossl"
58 .TH OPENSSL-VERIFY 1ossl 2025-09-30 3.5.4 OpenSSL
64 openssl\-verify \- certificate verification command
68 [\fB\-help\fR]
69 [\fB\-CRLfile\fR \fIfilename\fR|\fIuri\fR]
70 [\fB\-crl_download\fR]
71 [\fB\-show_chain\fR]
72 [\fB\-verbose\fR]
73 [\fB\-trusted\fR \fIfilename\fR|\fIuri\fR]
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H A Dopenssl-engine.11 .\" -*- mode: troff; coding: utf-8 -*-
57 .IX Title "OPENSSL-ENGINE 1ossl"
58 .TH OPENSSL-ENGINE 1ossl 2025-09-30 3.5.4 OpenSSL
64 openssl\-engine \- load and query engines
67 \&\fBopenssl engine\fR
68 [\fB\-help\fR]
69 [\fB\-v\fR]
70 [\fB\-vv\fR]
71 [\fB\-vvv\fR]
72 [\fB\-vvvv\fR]
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H A Dopenssl.11 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL 1ossl 2025-09-30 3.5.4 OpenSSL
64 openssl \- OpenSSL command line program
72 \&\fBopenssl\fR \fBno\-\fR\fIXXX\fR [ \fIoptions\fR ]
74 \&\fBopenssl\fR \fB\-help\fR | \fB\-version\fR
103 (e.g., \fBopenssl\-x509\fR\|(1)). The subcommand \fBopenssl\-list\fR\|(1) may be used to list
106 The command \fBno\-\fR\fIXXX\fR tests whether a command of the
108 returns 0 (success) and prints \fBno\-\fR\fIXXX\fR; otherwise it returns 1
113 availability of ciphers in the \fBopenssl\fR program. (\fBno\-\fR\fIXXX\fR is
114 not able to detect pseudo-commands such as \fBquit\fR,
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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dallwinner,sun50i-a64-de2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A64 Display Engine Bus
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 pattern: "^bus(@[0-9a-f]+)?$"
17 "#address-cells":
20 "#size-cells":
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/freebsd/crypto/openssl/crypto/engine/
H A Dtb_asnmth.c2 * Copyright 2006-2023 The OpenSSL Project Authors. All Rights Reserved.
10 /* We need to use some engine deprecated APIs */
21 * defaults (etc), will display brief debugging summaries to stderr with the
28 void ENGINE_unregister_pkey_asn1_meths(ENGINE *e) in ENGINE_unregister_pkey_asn1_meths()
38 int ENGINE_register_pkey_asn1_meths(ENGINE *e) in ENGINE_register_pkey_asn1_meths()
40 if (e->pkey_asn1_meths) { in ENGINE_register_pkey_asn1_meths()
42 int num_nids = e->pkey_asn1_meths(e, NULL, &nids, 0); in ENGINE_register_pkey_asn1_meths()
53 ENGINE *e; in ENGINE_register_all_pkey_asn1_meths()
59 int ENGINE_set_default_pkey_asn1_meths(ENGINE *e) in ENGINE_set_default_pkey_asn1_meths()
61 if (e->pkey_asn1_meths) { in ENGINE_set_default_pkey_asn1_meths()
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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dmediatek,gce-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Global Command Engine Mailbox
10 - Houlong Wei <houlong.wei@mediatek.com>
13 The Global Command Engine (GCE) is used to help read/write registers with
14 critical time limitation, such as updating display configuration during the
20 - enum:
21 - mediatek,mt6779-gce
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