Lines Matching +full:display +full:- +full:engine
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller interrupt controller
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
19 Alternatively the un-masked trigger signals for all HW events are provided,
26 - Liu Ying <victor.liu@nxp.com>
30 const: fsl,imx8qxp-dc-intc
38 interrupt-controller: true
40 "#interrupt-cells":
45 - description: store9 shadow load interrupt(blit engine)
46 - description: store9 frame complete interrupt(blit engine)
47 - description: store9 sequence complete interrupt(blit engine)
48 - description:
50 (display controller, content stream 0)
51 - description:
53 (display controller, content stream 0)
54 - description:
56 (display controller, content stream 0)
57 - description:
59 (display controller, safety stream 0)
60 - description:
62 (display controller, safety stream 0)
63 - description:
65 (display controller, safety stream 0)
66 - description:
68 (display controller, content stream 1)
69 - description:
71 (display controller, content stream 1)
72 - description:
74 (display controller, content stream 1)
75 - description:
77 (display controller, safety stream 1)
78 - description:
80 (display controller, safety stream 1)
81 - description:
83 (display controller, safety stream 1)
84 - description:
86 (display controller, display stream 0)
87 - description:
89 (display controller, display stream 0)
90 - description:
92 (display controller, display stream 0)
93 - description:
95 (display controller, display stream 0)
96 - description:
98 (display controller, display stream 0)
99 - description:
101 (display controller, display stream 0)
102 - description:
104 (display controller, display stream 0)
105 - description:
107 (display controller, display stream 0)
108 - description:
110 (display controller, display stream 0)
111 - description:
113 (display controller, display stream 0)
114 - description:
116 (display controller, display stream 1)
117 - description:
119 (display controller, display stream 1)
120 - description:
122 (display controller, display stream 1)
123 - description:
125 (display controller, display stream 1)
126 - description:
128 (display controller, display stream 1)
129 - description:
131 (display controller, display stream 1)
132 - description:
134 (display controller, display stream 1)
135 - description:
137 (display controller, display stream 1)
138 - description:
140 (display controller, display stream 1)
141 - description:
143 (display controller, display stream 1)
144 - description: reserved
145 - description:
147 - description:
149 - description:
151 - description:
153 - description:
155 - description:
157 (display controller, safety stream 0)
158 - description:
160 (display controller, safety stream 0)
161 - description:
163 (display controller, content stream 0)
164 - description:
166 (display controller, content stream 0)
167 - description:
169 (display controller, safety stream 1)
170 - description:
172 (display controller, safety stream 1)
173 - description:
175 (display controller, content stream 1)
176 - description:
178 (display controller, content stream 1)
181 interrupt-names:
183 - const: store9_shdload
184 - const: store9_framecomplete
185 - const: store9_seqcomplete
186 - const: extdst0_shdload
187 - const: extdst0_framecomplete
188 - const: extdst0_seqcomplete
189 - const: extdst4_shdload
190 - const: extdst4_framecomplete
191 - const: extdst4_seqcomplete
192 - const: extdst1_shdload
193 - const: extdst1_framecomplete
194 - const: extdst1_seqcomplete
195 - const: extdst5_shdload
196 - const: extdst5_framecomplete
197 - const: extdst5_seqcomplete
198 - const: disengcfg_shdload0
199 - const: disengcfg_framecomplete0
200 - const: disengcfg_seqcomplete0
201 - const: framegen0_int0
202 - const: framegen0_int1
203 - const: framegen0_int2
204 - const: framegen0_int3
205 - const: sig0_shdload
206 - const: sig0_valid
207 - const: sig0_error
208 - const: disengcfg_shdload1
209 - const: disengcfg_framecomplete1
210 - const: disengcfg_seqcomplete1
211 - const: framegen1_int0
212 - const: framegen1_int1
213 - const: framegen1_int2
214 - const: framegen1_int3
215 - const: sig1_shdload
216 - const: sig1_valid
217 - const: sig1_error
218 - const: reserved
219 - const: cmdseq_error
220 - const: comctrl_sw0
221 - const: comctrl_sw1
222 - const: comctrl_sw2
223 - const: comctrl_sw3
224 - const: framegen0_primsync_on
225 - const: framegen0_primsync_off
226 - const: framegen0_secsync_on
227 - const: framegen0_secsync_off
228 - const: framegen1_primsync_on
229 - const: framegen1_primsync_off
230 - const: framegen1_secsync_on
231 - const: framegen1_secsync_off
235 - compatible
236 - reg
237 - clocks
238 - interrupt-controller
239 - "#interrupt-cells"
240 - interrupts
241 - interrupt-names
246 - |
247 #include <dt-bindings/clock/imx8-lpcg.h>
249 interrupt-controller@56180040 {
250 compatible = "fsl,imx8qxp-dc-intc";
253 interrupt-controller;
254 interrupt-parent = <&dc0_irqsteer>;
255 #interrupt-cells = <1>;
269 interrupt-names = "store9_shdload",