Lines Matching +full:display +full:- +full:engine
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Display Controller Display Engine
10 All Processing Units that operate in a display clock domain. Pixel pipeline
11 is driven by a video timing and cannot be stalled. Implements all display
15 - Liu Ying <victor.liu@nxp.com>
19 const: fsl,imx8qxp-dc-display-engine
24 reg-names:
26 - const: top
27 - const: cfg
35 interrupt-names:
37 - const: shdload
38 - const: framecomplete
39 - const: seqcomplete
41 power-domains:
44 "#address-cells":
47 "#size-cells":
53 "^dither@[0-9a-f]+$":
59 const: fsl,imx8qxp-dc-dither
61 "^framegen@[0-9a-f]+$":
67 const: fsl,imx8qxp-dc-framegen
69 "^gammacor@[0-9a-f]+$":
75 const: fsl,imx8qxp-dc-gammacor
77 "^matrix@[0-9a-f]+$":
83 const: fsl,imx8qxp-dc-matrix
85 "^signature@[0-9a-f]+$":
91 const: fsl,imx8qxp-dc-signature
93 "^tcon@[0-9a-f]+$":
99 const: fsl,imx8qxp-dc-tcon
102 - compatible
103 - reg
104 - reg-names
105 - interrupts
106 - interrupt-names
107 - power-domains
108 - "#address-cells"
109 - "#size-cells"
110 - ranges
115 - |
116 #include <dt-bindings/clock/imx8-lpcg.h>
117 #include <dt-bindings/firmware/imx/rsrc.h>
119 display-engine@5618b400 {
120 compatible = "fsl,imx8qxp-dc-display-engine";
122 reg-names = "top", "cfg";
123 interrupt-parent = <&dc0_intc>;
125 interrupt-names = "shdload", "framecomplete", "seqcomplete";
126 power-domains = <&pd IMX_SC_R_DC_0_PLL_0>;
127 #address-cells = <1>;
128 #size-cells = <1>;
132 compatible = "fsl,imx8qxp-dc-framegen";
135 interrupt-parent = <&dc0_intc>;
137 interrupt-names = "int0", "int1", "int2", "int3",
143 compatible = "fsl,imx8qxp-dc-tcon";
148 remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_disp0>;