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/linux/drivers/gpu/drm/msm/dp/
H A Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
19 * msm_dp_bridge_detect - callback to determine if connector is connected
20 * @bridge: Pointer to drm bridge structure
21 * Returns: Bridge's 'is connected' status
24 msm_dp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) in msm_dp_bridge_detect() argument
28 dp = to_dp_bridge(bridge)->msm_dp_display; in msm_dp_bridge_detect()
30 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in msm_dp_bridge_detect()
31 str_true_false(dp->link_ready)); in msm_dp_bridge_detect()
33 return (dp->link_ready) ? connector_status_connected : in msm_dp_bridge_detect()
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H A Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
15 #include <drm/display/drm_dp_aux_bus.h>
16 #include <drm/display/drm_hdmi_audio_helper.h>
190 { .compatible = "qcom,sa8775p-dp", .data = &msm_dp_desc_sa8775p },
191 { .compatible = "qcom,sc7180-dp", .data = &msm_dp_desc_sc7180 },
192 { .compatible = "qcom,sc7280-dp", .data = &msm_dp_desc_sc7280 },
193 { .compatible = "qcom,sc7280-edp", .data = &msm_dp_desc_sc7280 },
194 { .compatible = "qcom,sc8180x-dp", .data = &msm_dp_desc_sc8180x },
195 { .compatible = "qcom,sc8180x-edp", .data = &msm_dp_desc_sc8180x },
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_drv.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 * DOC: ST-Ericsson MCDE Driver
11 * The MCDE (short for multi-channel display engine) is a graphics
15 * ST-Ericsson U8500 where is was used for mass-market deployments
18 * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for
22 * The hardware has four display pipes, and the layout is a little
25 * Memory -> Overlay -> Channel -> FIFO -> 8 formatters -> DSI/DPI
26 * External 0..5 0..3 A,B, 6 x DSI bridge
36 * DPI port, it is possible to configure up to 4 display pipelines
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pxl2dpi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
25 const: fsl,imx8qxp-pxl2dpi
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H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358775.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge
10 - Vinay Simha BN <simhavcs@gmail.com>
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
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H A Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
19 display controllers.
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
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H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
10 - Liu Ying <victor.liu@nxp.com>
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
23 LDB split mode to support a dual link LVDS display. The channel indexes
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
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H A Dti,dlpc3433.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DLPC3433 MIPI DSI to DMD bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Christopher Vollo <chris@renewoutreach.org>
14 TI DLPC3433 is a MIPI DSI based display controller bridge
30 - 0x1b
31 - 0x1d
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H A Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
29 description: GPIO specifier for GPIO1 pin on bridge (active low).
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H A Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
13 The TC358767/TC358867/TC9595 is bridge device which
19 - items:
20 - enum:
21 - toshiba,tc358867
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H A Danalogix,dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analogix Display Port bridge
10 - Rob Herring <robh@kernel.org>
21 clock-names: true
25 phy-names:
28 force-hpd:
34 hpd-gpios:
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H A Dgoogle,cros-ec-anx7688.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
10 - Nicolas Boichat <drinkcat@chromium.org>
13 ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
14 DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
16 (See google,cros-ec.yaml). It is accessed using I2C tunneling through
18 (See google,cros-ec-i2c-tunnel.yaml).
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H A Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
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/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx6q-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6q-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale LVDS Display Bridge (ldb)
10 The LVDS Display Bridge device tree node contains up to two lvds-channel
11 nodes describing each of the two LVDS encoder channels of the bridge.
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,imx53-ldb
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/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Zheng Yang <zhengyang@rock-chips.com>
9 #include <drm/display/drm_hdmi_helper.h>
10 #include <drm/display/drm_hdmi_state_helper.h>
28 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
52 struct drm_bridge bridge; member
63 static struct rk3066_hdmi *bridge_to_rk3066_hdmi(struct drm_bridge *bridge) in bridge_to_rk3066_hdmi() argument
65 return container_of(bridge, struct rk3066_hdmi, bridge); in bridge_to_rk3066_hdmi()
70 return readl_relaxed(hdmi->regs + offset); in hdmi_readb()
75 writel_relaxed(val, hdmi->regs + offset); in hdmi_writeb()
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/linux/drivers/gpu/drm/tve200/
H A Dtve200_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2006-2008 Intel Corporation
21 * 8-bit BT.656 interface.
23 * This is a very basic YUV display driver. The datasheet specifies that
31 #include <linux/dma-buf.h>
67 struct tve200_drm_dev_private *priv = dev->dev_private; in tve200_modeset_init()
69 struct drm_bridge *bridge; in tve200_modeset_init() local
73 mode_config = &dev->mode_config; in tve200_modeset_init()
74 mode_config->funcs = &mode_config_funcs; in tve200_modeset_init()
75 mode_config->min_width = 352; in tve200_modeset_init()
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/linux/drivers/gpu/drm/bridge/
H A Dmegachips-stdpxxxx-ge-b850v3-fw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
4 * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
11 * display bridge of the GE B850v3. There are two physical bridges on the video
19 * Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
61 struct drm_bridge bridge; member
71 struct i2c_adapter *adapter = client->adapter; in stdp2690_read_block()
76 .addr = client->addr, in stdp2690_read_block()
81 .addr = client->addr, in stdp2690_read_block()
89 return -1; in stdp2690_read_block()
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_audio.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <drm/display/drm_hdmi_helper.h>
8 #include <drm/display/drm_hdmi_state_helper.h>
12 #include <sound/hdmi-codec.h>
18 struct hdmi_audio *audio = &hdmi->audio; in msm_hdmi_audio_update()
19 bool enabled = audio->enabled; in msm_hdmi_audio_update()
23 if (!hdmi->connector->display_info.is_hdmi) in msm_hdmi_audio_update()
24 return -EINVAL; in msm_hdmi_audio_update()
27 audio->enabled, audio->channels, audio->rate); in msm_hdmi_audio_update()
29 DBG("video: power_on=%d, pixclock=%lu", hdmi->power_on, hdmi->pixclock); in msm_hdmi_audio_update()
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H A Dhdmi_bridge.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <drm/display/drm_hdmi_helper.h>
11 #include <drm/display/drm_hdmi_state_helper.h>
16 static void msm_hdmi_power_on(struct drm_bridge *bridge) in msm_hdmi_power_on() argument
18 struct drm_device *dev = bridge->dev; in msm_hdmi_power_on()
19 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); in msm_hdmi_power_on()
20 struct hdmi *hdmi = hdmi_bridge->hdmi; in msm_hdmi_power_on()
23 pm_runtime_resume_and_get(&hdmi->pdev->dev); in msm_hdmi_power_on()
25 if (hdmi->extp_clk) { in msm_hdmi_power_on()
26 DBG("pixclock: %lu", hdmi->pixclock); in msm_hdmi_power_on()
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/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX drm driver - LVDS display bridge
11 #include <linux/media-bus-format.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
31 #include <drm/bridge/imx.h>
33 #include "imx-drm.h"
35 #define DRIVER_NAME "imx-ldb"
64 struct drm_bridge *bridge; member
73 return container_of(e, struct imx_ldb_encoder, encoder)->channel; in enc_to_imx_ldb_ch()
87 struct clk *clk_sel[4]; /* parent of display clock */
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/linux/Documentation/devicetree/bindings/display/panel/
H A Draspberrypi,7inch-touchscreen.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/raspberrypi,7inch-touchscreen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
11 - Thierry Reding <thierry.reding@gmail.com>
16 - TC358762 DSI->DPI bridge
17 - Atmel microcontroller on I2C for power sequencing the DSI bridge and
19 - Touchscreen controller on I2C for touch input
21 and this binding covers the DSI display parts but not its touch input.
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/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c1 // SPDX-License-Identifier: GPL-2.0
30 for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) { in komeda_crtc_get_color_config()
31 if (conn_st->crtc != crtc_st->crtc) in komeda_crtc_get_color_config()
34 conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8; in komeda_crtc_get_color_config()
35 conn_color_formats &= conn->display_info.color_formats; in komeda_crtc_get_color_config()
53 if (!kcrtc_st->base.active) { in komeda_crtc_update_clock_ratio()
54 kcrtc_st->clock_ratio = 0; in komeda_crtc_update_clock_ratio()
58 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL; in komeda_crtc_update_clock_ratio()
61 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk); in komeda_crtc_update_clock_ratio()
65 * komeda_crtc_atomic_check - build display output data flow
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_dp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Samsung SoC DP (Display Port) interface driver.
21 #include <drm/bridge/analogix_dp.h>
52 struct drm_encoder *encoder = &dp->encoder; in exynos_dp_crtc_clock_enable()
54 if (!encoder->crtc) in exynos_dp_crtc_clock_enable()
55 return -EPERM; in exynos_dp_crtc_clock_enable()
57 exynos_drm_pipe_clk_enable(to_exynos_crtc(encoder->crtc), enable); in exynos_dp_crtc_clock_enable()
78 if (dp->plat_data.panel) in exynos_dp_get_modes()
81 mode = drm_mode_create(connector->dev); in exynos_dp_get_modes()
83 DRM_DEV_ERROR(dp->dev, in exynos_dp_get_modes()
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
21 #include <linux/dma-mapping.h>
24 #include <media/cec-notifier.h>
26 #include <linux/media-bus-format.h>
29 #include <drm/bridge/dw_hdmi.h>
30 #include <drm/display/drm_hdmi_helper.h>
31 #include <drm/display/drm_scdc_helper.h>
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