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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sdm670-mdss.yaml82 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
93 power-domains = <&dispcc MDSS_GDSC>;
96 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_AXI_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
160 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
161 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
162 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,sdm845-mdss.yaml84 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
96 power-domains = <&dispcc MDSS_GDSC>;
99 <&dispcc DISP_CC_MDSS_MDP_CLK>;
117 <&dispcc DISP_CC_MDSS_AHB_CLK>,
118 <&dispcc DISP_CC_MDSS_AXI_CLK>,
119 <&dispcc DISP_CC_MDSS_MDP_CLK>,
120 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,sc7180-mdss.yaml26 - description: Display AHB clock from dispcc
90 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_ROT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8450-mdss.yaml82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_CLK>,
132 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6350-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
98 power-domains = <&dispcc MDSS_GDSC>;
102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_ROT_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_MDP_CLK>,
125 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
[all …]
H A Dqcom,sm8250-mdss.yaml90 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
106 power-domains = <&dispcc MDSS_GDSC>;
108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>;
130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
197 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
198 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm8150-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
129 <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
194 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
195 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm6125-mdss.yaml78 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
94 <&dispcc DISP_CC_MDSS_AHB_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
100 power-domains = <&dispcc MDSS_GDSC>;
118 <&dispcc DISP_CC_MDSS_AHB_CLK>,
119 <&dispcc DISP_CC_MDSS_ROT_CLK>,
120 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
121 <&dispcc DISP_CC_MDSS_MDP_CLK>,
122 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
131 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6375-mdss.yaml80 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
89 power-domains = <&dispcc MDSS_GDSC>;
92 <&dispcc DISP_CC_MDSS_AHB_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_ROT_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6115-mdss.yaml80 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
92 power-domains = <&dispcc MDSS_GDSC>;
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_MDP_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_ROT_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
146 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
147 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,qcm2290-mdss.yaml82 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
95 power-domains = <&dispcc MDSS_GDSC>;
98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
120 <&dispcc DISP_CC_MDSS_AHB_CLK>,
121 <&dispcc DISP_CC_MDSS_MDP_CLK>,
122 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
123 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
154 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
155 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
156 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,qcm2290-dpu.yaml31 - description: Display AHB clock from dispcc
32 - description: Display core clock from dispcc
33 - description: Display lut clock from dispcc
34 - description: Display vsync clock from dispcc
55 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
66 <&dispcc DISP_CC_MDSS_AHB_CLK>,
67 <&dispcc DISP_CC_MDSS_MDP_CLK>,
68 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
69 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6115-dpu.yaml57 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_MDP_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
71 <&dispcc DISP_CC_MDSS_ROT_CLK>,
72 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sc7180-dpu.yaml81 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
93 <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&dispcc DISP_CC_MDSS_ROT_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
96 <&dispcc DISP_CC_MDSS_MDP_CLK>,
97 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sdm845-dpu.yaml57 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_AXI_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_CLK>,
71 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddp-controller.yaml338 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
350 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
351 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
352 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
353 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
354 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
359 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
360 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,dispcc-sm8x50.yaml4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
26 - qcom,sm8250-dispcc
27 - qcom,sm8350-dispcc
86 const: qcom,sc8180x-dispcc
101 compatible = "qcom,sm8250-dispcc";
H A Dqcom,sa8775p-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
16 See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
H A Dqcom,dispcc-sc8280xp.yaml4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
17 include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
/linux/include/dt-bindings/clock/
H A Dqcom,sm7150-dispcc.h11 /* DISPCC clock registers */
56 /* DISPCC resets */
59 /* DISPCC GDSCR */
H A Dqcom,dispcc-sc8280xp.h9 /* DISPCC clocks */
92 /* DISPCC resets */
96 /* DISPCC GDSCs */
/linux/arch/arm64/boot/dts/qcom/
H A Dagatti.dtsi8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
1944 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1949 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
1951 power-domains = <&dispcc MDSS_GDSC>;
1978 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1979 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1980 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1981 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2041 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2042 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dhamoa.dtsi9 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
5560 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5562 <&dispcc DISP_CC_MDSS_MDP_CLK>;
5564 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
5576 power-domains = <&dispcc MDSS_GDSC>;
5599 <&dispcc DISP_CC_MDSS_AHB_CLK>,
5600 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
5601 <&dispcc DISP_CC_MDSS_MDP_CLK>,
5602 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
5690 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
[all …]
H A Dmonaco.dtsi10 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
5744 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
5746 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>;
5748 resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>;
5760 power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>;
5782 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
5783 <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
5784 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>,
5785 <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
5792 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dsa8155p.dtsi16 &dispcc {

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