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/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sdm670-mdss.yaml82 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
93 power-domains = <&dispcc MDSS_GDSC>;
96 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_AXI_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
160 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
161 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
162 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,sdm845-mdss.yaml84 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
96 power-domains = <&dispcc MDSS_GDSC>;
99 <&dispcc DISP_CC_MDSS_MDP_CLK>;
117 <&dispcc DISP_CC_MDSS_AHB_CLK>,
118 <&dispcc DISP_CC_MDSS_AXI_CLK>,
119 <&dispcc DISP_CC_MDSS_MDP_CLK>,
120 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,sc7180-mdss.yaml26 - description: Display AHB clock from dispcc
90 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_ROT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8450-mdss.yaml82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_CLK>,
132 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6350-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
98 power-domains = <&dispcc MDSS_GDSC>;
102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_ROT_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_MDP_CLK>,
125 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
[all …]
H A Dqcom,sm8250-mdss.yaml90 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
106 power-domains = <&dispcc MDSS_GDSC>;
108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>;
130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
197 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
198 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm8150-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
129 <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
194 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
195 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm6125-mdss.yaml78 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
94 <&dispcc DISP_CC_MDSS_AHB_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
100 power-domains = <&dispcc MDSS_GDSC>;
118 <&dispcc DISP_CC_MDSS_AHB_CLK>,
119 <&dispcc DISP_CC_MDSS_ROT_CLK>,
120 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
121 <&dispcc DISP_CC_MDSS_MDP_CLK>,
122 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
131 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6375-mdss.yaml80 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
89 power-domains = <&dispcc MDSS_GDSC>;
92 <&dispcc DISP_CC_MDSS_AHB_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_ROT_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8350-mdss.yaml91 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
110 power-domains = <&dispcc MDSS_GDSC>;
111 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
113 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
116 <&dispcc DISP_CC_MDSS_MDP_CLK>;
137 <&dispcc DISP_CC_MDSS_AHB_CLK>,
138 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
139 <&dispcc DISP_CC_MDSS_MDP_CLK>,
140 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
148 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm6115-mdss.yaml80 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
92 power-domains = <&dispcc MDSS_GDSC>;
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_MDP_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_ROT_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
146 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
147 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,qcm2290-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
100 power-domains = <&dispcc MDSS_GDSC>;
103 <&dispcc DISP_CC_MDSS_MDP_CLK>;
125 <&dispcc DISP_CC_MDSS_AHB_CLK>,
126 <&dispcc DISP_CC_MDSS_MDP_CLK>,
127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
159 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
160 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
161 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
[all …]
H A Dqcom,qcm2290-dpu.yaml35 - description: Display AHB clock from dispcc
36 - description: Display core clock from dispcc
37 - description: Display lut clock from dispcc
38 - description: Display vsync clock from dispcc
59 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
70 <&dispcc DISP_CC_MDSS_AHB_CLK>,
71 <&dispcc DISP_CC_MDSS_MDP_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6115-dpu.yaml57 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_MDP_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
71 <&dispcc DISP_CC_MDSS_ROT_CLK>,
72 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sc7180-dpu.yaml81 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
93 <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&dispcc DISP_CC_MDSS_ROT_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
96 <&dispcc DISP_CC_MDSS_MDP_CLK>,
97 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,qcs8300-mdss.yaml85 #include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
200 clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>,
201 <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>,
202 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>,
203 <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>,
204 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
212 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>,
213 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>;
265 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>,
280 clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
[all …]
H A Dqcom,sdm845-dpu.yaml57 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_AXI_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_CLK>,
71 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddp-controller.yaml356 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
368 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
369 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
370 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
371 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
372 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
377 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
378 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
H A Ddsi-controller-main.yaml442 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
457 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
458 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
459 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
460 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
461 <&dispcc DISP_CC_MDSS_AHB_CLK>,
462 <&dispcc DISP_CC_MDSS_AXI_CLK>;
473 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8550-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
18 - include/dt-bindings/clock/qcom,kaanapali-dispcc.h
19 - include/dt-bindings/clock/qcom,nord-dispcc.h
20 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
21 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
22 - include/dt-bindings/clock/qcom,sm8750-dispcc.h
23 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
28 - qcom,kaanapali-dispcc
31 - qcom,sar2130p-dispcc
32 - qcom,sm8550-dispcc
[all …]
H A Dqcom,qcm2290-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
16 See also: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
23 - qcom,shikra-dispcc
24 - const: qcom,qcm2290-dispcc
26 - qcom,qcm2290-dispcc
64 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
69 compatible = "qcom,qcm2290-dispcc";
H A Dqcom,dispcc-sm6125.yaml4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
16 See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h
21 - qcom,sm6125-dispcc
72 compatible = "qcom,sm6125-dispcc";
/linux/drivers/clk/qcom/
H A DMakefile24 obj-$(CONFIG_CLK_ELIZA_DISPCC) += dispcc-eliza.o
29 obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
39 obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
52 obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
108 obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
109 obj-$(CONFIG_QCS_DISPCC_615) += dispcc-qcs615.o
124 obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
125 obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
126 obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
148 obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
[all …]
/linux/include/dt-bindings/clock/
H A Dqcom,sm7150-dispcc.h11 /* DISPCC clock registers */
56 /* DISPCC resets */
59 /* DISPCC GDSCR */
H A Dqcom,dispcc-sc8280xp.h9 /* DISPCC clocks */
92 /* DISPCC resets */
96 /* DISPCC GDSCs */

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