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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,sdm845-mdss.yaml84 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
96 power-domains = <&dispcc MDSS_GDSC>;
99 <&dispcc DISP_CC_MDSS_MDP_CLK>;
117 <&dispcc DISP_CC_MDSS_AHB_CLK>,
118 <&dispcc DISP_CC_MDSS_AXI_CLK>,
119 <&dispcc DISP_CC_MDSS_MDP_CLK>,
120 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158 <&dispcc DISP_CC_MDSS_PCLK0_CL
[all...]
H A Dqcom,sc7280-mdss.yaml26 - description: Display AHB clock from dispcc
100 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
113 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
115 <&dispcc DISP_CC_MDSS_AHB_CLK>,
116 <&dispcc DISP_CC_MDSS_MDP_CLK>;
142 <&dispcc DISP_CC_MDSS_AHB_CLK>,
143 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
144 <&dispcc DISP_CC_MDSS_MDP_CLK>,
145 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
193 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CL
[all...]
H A Dqcom,sc7180-mdss.yaml26 - description: Display AHB clock from dispcc
90 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 <&dispcc DISP_CC_MDSS_AHB_CLK>,
106 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_ROT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CL
[all...]
H A Dqcom,sm8450-mdss.yaml82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
129 <&dispcc DISP_CC_MDSS_AHB_CLK>,
130 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_CLK>,
132 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CL
[all...]
H A Dqcom,sm8550-mdss.yaml82 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
98 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
100 power-domains = <&dispcc MDSS_GDSC>;
102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
105 <&dispcc DISP_CC_MDSS_MDP_CLK>;
126 <&dispcc DISP_CC_MDSS_AHB_CLK>,
127 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
128 <&dispcc DISP_CC_MDSS_MDP_CLK>,
129 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
137 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CL
[all...]
H A Dqcom,sm6350-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
98 power-domains = <&dispcc MDSS_GDSC>;
102 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_ROT_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_MDP_CLK>,
125 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
[all …]
H A Dqcom,sm8250-mdss.yaml90 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
106 power-domains = <&dispcc MDSS_GDSC>;
108 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
111 <&dispcc DISP_CC_MDSS_MDP_CLK>;
130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
136 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
197 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
198 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CL
[all...]
H A Dqcom,sm8150-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
103 power-domains = <&dispcc MDSS_GDSC>;
105 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
108 <&dispcc DISP_CC_MDSS_MDP_CLK>;
127 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
129 <&dispcc DISP_CC_MDSS_MDP_CLK>,
130 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
133 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
194 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
195 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
[all …]
H A Dqcom,sm6375-mdss.yaml80 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
89 power-domains = <&dispcc MDSS_GDSC>;
92 <&dispcc DISP_CC_MDSS_AHB_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_ROT_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
[all …]
H A Dqcom,sm8350-mdss.yaml87 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
103 power-domains = <&dispcc MDSS_GDSC>;
104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
106 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
109 <&dispcc DISP_CC_MDSS_MDP_CLK>;
130 <&dispcc DISP_CC_MDSS_AHB_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
141 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CL
[all...]
H A Dqcom,sm6115-mdss.yaml80 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
92 power-domains = <&dispcc MDSS_GDSC>;
95 <&dispcc DISP_CC_MDSS_MDP_CLK>;
112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_MDP_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_ROT_CLK>,
116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
146 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
147 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CL
[all...]
H A Dqcom,qcm2290-mdss.yaml82 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
95 power-domains = <&dispcc MDSS_GDSC>;
98 <&dispcc DISP_CC_MDSS_MDP_CLK>;
121 <&dispcc DISP_CC_MDSS_AHB_CLK>,
122 <&dispcc DISP_CC_MDSS_MDP_CLK>,
123 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
155 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
156 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
157 <&dispcc DISP_CC_MDSS_PCLK0_CL
[all...]
H A Dqcom,qcm2290-dpu.yaml31 - description: Display AHB clock from dispcc
32 - description: Display core clock from dispcc
33 - description: Display lut clock from dispcc
34 - description: Display vsync clock from dispcc
55 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
66 <&dispcc DISP_CC_MDSS_AHB_CLK>,
67 <&dispcc DISP_CC_MDSS_MDP_CLK>,
68 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
69 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddpu-qcm2290.yaml97 - description: Display AHB clock from dispcc
98 - description: Display core clock from dispcc
99 - description: Display lut clock from dispcc
100 - description: Display vsync clock from dispcc
161 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
173 power-domains = <&dispcc MDSS_GDSC>;
176 <&dispcc DISP_CC_MDSS_MDP_CLK>;
197 <&dispcc DISP_CC_MDSS_AHB_CLK>,
198 <&dispcc DISP_CC_MDSS_MDP_CLK>,
199 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
[all …]
H A Ddpu-sc7180.yaml34 - description: Display AHB clock from dispcc
166 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
178 power-domains = <&dispcc MDSS_GDSC>;
180 <&dispcc DISP_CC_MDSS_AHB_CLK>,
181 <&dispcc DISP_CC_MDSS_MDP_CLK>;
202 <&dispcc DISP_CC_MDSS_AHB_CLK>,
203 <&dispcc DISP_CC_MDSS_ROT_CLK>,
204 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
205 <&dispcc DISP_CC_MDSS_MDP_CLK>,
206 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddpu-sc7280.yaml33 - description: Display AHB clock from dispcc
164 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
176 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
178 <&dispcc DISP_CC_MDSS_AHB_CLK>,
179 <&dispcc DISP_CC_MDSS_MDP_CLK>;
203 <&dispcc DISP_CC_MDSS_AHB_CLK>,
204 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
205 <&dispcc DISP_CC_MDSS_MDP_CLK>,
206 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm6115-dpu.yaml57 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_MDP_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
71 <&dispcc DISP_CC_MDSS_ROT_CLK>,
72 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddp-controller.yaml182 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
203 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
H A Dqcom,sc7180-dpu.yaml81 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
93 <&dispcc DISP_CC_MDSS_AHB_CLK>,
94 <&dispcc DISP_CC_MDSS_ROT_CLK>,
95 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
96 <&dispcc DISP_CC_MDSS_MDP_CLK>,
97 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8350-dpu.yaml50 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
64 <&dispcc DISP_CC_MDSS_AHB_CLK>,
65 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
66 <&dispcc DISP_CC_MDSS_MDP_CLK>,
67 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
75 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8550-dpu.yaml57 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
70 <&dispcc DISP_CC_MDSS_AHB_CLK>,
71 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_CLK>,
73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
81 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Dqcom,sm8450-dpu.yaml57 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
71 <&dispcc DISP_CC_MDSS_AHB_CLK>,
72 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
73 <&dispcc DISP_CC_MDSS_MDP_CLK>,
74 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
82 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
H A Ddpu-sdm845.yaml155 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
166 power-domains = <&dispcc MDSS_GDSC>;
169 <&dispcc DISP_CC_MDSS_MDP_CLK>;
186 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
187 <&dispcc DISP_CC_MDSS_AXI_CLK>,
188 <&dispcc DISP_CC_MDSS_MDP_CLK>,
189 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,dispcc-sm8x50.yaml4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
26 - qcom,sm8250-dispcc
27 - qcom,sm8350-dispcc
86 const: qcom,sc8180x-dispcc
101 compatible = "qcom,sm8250-dispcc";
H A Dqcom,sm8550-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
18 - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19 - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20 - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
25 - qcom,sm8550-dispcc
26 - qcom,sm8650-dispcc
27 - qcom,x1e80100-dispcc
74 compatible = "qcom,sm8550-dispcc";

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