1*ca3a9106SDanila Tikhonov /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ca3a9106SDanila Tikhonov /* 3*ca3a9106SDanila Tikhonov * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4*ca3a9106SDanila Tikhonov * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5*ca3a9106SDanila Tikhonov * Copyright (c) 2024, David Wronek <david@mainlining.org> 6*ca3a9106SDanila Tikhonov */ 7*ca3a9106SDanila Tikhonov 8*ca3a9106SDanila Tikhonov #ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H 9*ca3a9106SDanila Tikhonov #define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H 10*ca3a9106SDanila Tikhonov 11*ca3a9106SDanila Tikhonov /* DISPCC clock registers */ 12*ca3a9106SDanila Tikhonov #define DISPCC_PLL0 0 13*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_AHB_CLK 1 14*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_AHB_CLK_SRC 2 15*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE0_CLK 3 16*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE0_CLK_SRC 4 17*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5 18*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE0_INTF_CLK 6 19*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE1_CLK 7 20*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE1_CLK_SRC 8 21*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9 22*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_BYTE1_INTF_CLK 10 23*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_AUX_CLK 11 24*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_AUX_CLK_SRC 12 25*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_CRYPTO_CLK 13 26*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14 27*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_LINK_CLK 15 28*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_LINK_CLK_SRC 16 29*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_LINK_INTF_CLK 17 30*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_PIXEL1_CLK 18 31*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19 32*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_PIXEL_CLK 20 33*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21 34*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_ESC0_CLK 22 35*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_ESC0_CLK_SRC 23 36*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_ESC1_CLK 24 37*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_ESC1_CLK_SRC 25 38*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_MDP_CLK 26 39*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_MDP_CLK_SRC 27 40*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_MDP_LUT_CLK 28 41*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_NON_GDSC_AHB_CLK 29 42*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_PCLK0_CLK 30 43*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_PCLK0_CLK_SRC 31 44*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_PCLK1_CLK 32 45*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_PCLK1_CLK_SRC 33 46*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_ROT_CLK 34 47*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_ROT_CLK_SRC 35 48*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_RSCC_AHB_CLK 36 49*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_RSCC_VSYNC_CLK 37 50*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_VSYNC_CLK 38 51*ca3a9106SDanila Tikhonov #define DISPCC_MDSS_VSYNC_CLK_SRC 39 52*ca3a9106SDanila Tikhonov #define DISPCC_XO_CLK_SRC 40 53*ca3a9106SDanila Tikhonov #define DISPCC_SLEEP_CLK 41 54*ca3a9106SDanila Tikhonov #define DISPCC_SLEEP_CLK_SRC 42 55*ca3a9106SDanila Tikhonov 56*ca3a9106SDanila Tikhonov /* DISPCC GDSCR */ 57*ca3a9106SDanila Tikhonov #define MDSS_GDSC 0 58*ca3a9106SDanila Tikhonov 59*ca3a9106SDanila Tikhonov #endif 60