Home
last modified time | relevance | path

Searched +full:default +full:- +full:sample +full:- +full:phase (Results 1 – 25 of 91) sorted by relevance

1234

/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Drockchip-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
20 - Heiko Stuebner <heiko@sntech.de>
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
30 - items:
[all …]
H A Dhisilicon,hi3798cv200-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <forbidden405@outlook.com>
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
26 - description: bus interface unit clock
27 - description: card interface unit clock
28 - description: card input sample phase clock
[all …]
H A Dmmci.txt11 - compatible : contains "arm,pl18x", "arm,primecell".
12 - vmmc-supply : phandle to the regulator device tree node, mentioned
16 - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
18 - resets : phandle to internal reset line.
20 - vqmmc-supply : phandle to the regulator device tree node, mentioned
23 - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
24 - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
25 - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
26 - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
27 - st,sig-dir-cmd : cmd signal direction pin used for CMD.
[all …]
/freebsd/usr.bin/beep/
H A Dbeep.c1 /*-
68 * "phase" should be in the range [0.0f .. 1.0f>
71 * The return value is in the range [-1.0f .. 1.0f]
74 wave_function_16(float phase, float power) in wave_function_16() argument
76 uint16_t x = phase * (1U << 16); in wave_function_16()
92 return (-1.0f); in wave_function_16()
93 default: in wave_function_16()
100 x ^= (mask - 1); in wave_function_16()
117 retval = (1.0f - retval) / 2.0f; in wave_function_16()
127 retval = -retval; in wave_function_16()
[all …]
/freebsd/contrib/ntp/ntpd/
H A Drefclock_irig.c2 * refclock_irig - audio IRIG-B/E demodulator/decoder
26 * Audio IRIG-B/E demodulator/decoder
29 * IRIG-B/E signals commonly produced by GPS receivers and other timing
30 * devices. The IRIG signal is an amplitude-modulated carrier with
31 * pulse-width modulated data bits. For IRIG-B, the carrier frequency is
32 * 1000 Hz and bit rate 100 b/s; for IRIG-E, the carrier frequenchy is
37 * kHz and mu-law companding. This is the same standard as used by the
43 * The program processes 8000-H
216 double phase, freq; /* logical clock phase and frequency */ global() member
417 double sample; /* codec sample */ irig_receive() local
508 irig_rf(struct peer * peer,double sample) irig_rf() argument
587 irig_base(struct peer * peer,double sample) irig_base() argument
[all...]
H A Drefclock_wwv.c2 * refclock_wwv - clock driver for NIST WWV/H time/frequency station
43 * kHz and mu-law companding. This is the same standard as used by the
53 * Report 97-8-1, University of Delaware, August 1997, 25 pp., available
61 * a nonzero ICOM ID select code. The C-IV trace is turned on if the
68 * port, where 0 is the mike port (default) and 1 is the line-in port.
71 * the monitor gain is set to a default value.
74 * CEVNT_PROP propagation failure - no stations heard
82 #define PRECISION (-1
514 double phase, freq; /* logical clock phase and frequency */ global() member
797 double sample; /* codec sample */ wwv_receive() local
[all...]
H A Dntp_refclock.c2 * ntp_refclock - processing support for reference clocks
45 * serial devices, process sample data, and to perform various debugging
53 * In addition, there may be a driver-specific unit structure used for
57 * which is used for all peer-specific processing and contains a
82 #if MAXSTAGE & (MAXSTAGE - 1)
89 pp->coderecv = (pp->coderecv + 1) % MAXSTAGE; in clk_add_sample()
90 if (pp->coderecv == pp->codeproc) in clk_add_sample()
91 pp->codepro in clk_add_sample()
1669 uint32_t phase; refclock_ppsaugment() local
[all...]
H A Drefclock_chu.c2 * refclock_chu - clock driver for Canadian CHU time/frequency station
44 * kHz and mu-law companding. This is the same standard as used by the
57 * maximum-likelihood technique which exploits the considerable degree
62 * consists of nine, ten-character bursts transmitted at 300 bps between
87 * the DUT1 (d in deciseconds), Gregorian year (yyyy), difference TAI -
101 * coincides with 0.5 - 9 * 11/300 = 0.170 second. Depending on the
110 * connections. With debugging enabled (-d on the ntpd command line),
113 * chuA or chuB followed by the status code and signal level (0-9999).
120 * where n is the number of characters in the burst (0-10), b the burst
121 * distance (0-40), f the field alignment (-1, 0, 1), s the
[all …]
/freebsd/contrib/ntp/html/
H A Ddiscipline.html1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
7 <!-- Changed by: stenn, 03-Jan-2020 -->
13 <!-- #BeginDate format:En2m -->3-Jan-2020 02:12<!-- #EndDate -->
18 <li class="inline"><a href="#pll">Phase-Lock Loop Operations</a></li>
24phase/frequency-lock feedback loop. It is an intricately crafted algorithm that automatically ada…
29sample <em>V<sub>d</sub></em>. Offset samples are processed by the clock filter to produce a filt…
30 …dates, while the phase predictor is the offset amortized over time in order to avoid setting the c…
33default poll exponent of 6 corresponds to a poll interval of 64 s and a time constant of 2048 s. …
34 … of the PLL are affected by the time constant and poll interval. At the default poll interval of …
[all …]
H A Dhowto.html1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
14 <!-- #BeginDate format:En2m -->10-Mar-2014 05:08<!-- #EndDate -->
24 <li class="inline"><a href="#pps">Pulse-per-Second Interface</a></li>
40 …<dd>Called at poll timeout, by default 64 s. Ordinarily, the driver will send a poll sequence to t…
42 …econd. This can be used for housekeeping functions. In the case with pulse-per-second (PPS) signal…
44-time timestamp to the <tt>refclock_process</tt> routine, which saves the computed offset in a 60-…
45 …roc</tt> structure, which contains for most drivers the decoded timecode, on-time timestamp, refer…
46 ….<i>u</i></tt>, where <i>t</i> is the clock type and <i>u</i> in the range 0-3 is used to distingu…
47-form driver name, short-form driver name and device name. The existing assignments are in the <a …
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Passes/
H A DPassBuilderPipelines.cpp1 //===- Construction of pass pipelines -------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
146 "enable-ml-inliner", cl::init(InliningAdvisorMode::Default), cl::Hidden,
147 cl::desc("Enable ML policy for inliner. Currently trained for -Oz only"),
148 cl::values(clEnumValN(InliningAdvisorMode::Default, "default",
149 "Heuristics-based inliner version"),
151 "Use development mode (runtime-loadable model)"),
153 "Use release mode (AOT-compiled model)")));
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drv1126-sonoff-ihost.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 stdout-path = "serial2:1500000n8";
19 vcc5v0_sys: regulator-vcc5v0-sys {
20 compatible = "regulator-fixed";
21 regulator-name = "vcc5v0_sys";
22 regulator-always-on;
23 regulator-boot-on;
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
28 sdio_pwrseq: pwrseq-sdio {
[all …]
H A Drv1126-edgeble-neu2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
14 vccio_flash: vccio-flash-regulator {
15 compatible = "regulator-fixed";
16 enable-activ
[all...]
H A Drv1126-edgeble-neu2-io.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "rv1126-edgeble-neu2.dtsi"
13 compatible = "edgeble,neural-compute-module-2-io",
14 "edgeble,neural-compute-module-2", "rockchip,rv1126";
21 stdout-path = "serial2:1500000n8";
24 vcc12v_dcin: vcc12v-dcin-regulator {
25 compatible = "regulator-fixed";
26 regulator-name = "vcc12v_dcin";
27 regulator-always-on;
[all …]
H A Drk3288-veyron-sdmmc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 sdcard-supply = <&vccio_sd>;
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
57 vcc9-supply = <&vcc_5v>;
61 regulator-name = "vccio_sd";
62 regulator-min-microvolt = <1800000>;
[all …]
/freebsd/usr.sbin/ppp/
H A Dppp.conf2 # PPP Sample Configuration File
10 default:
11 set log Phase Chat LCP IPCP CCP tun command
12 ident user-ppp VERSION
21 \"\" AT OK-AT-OK ATE1Q0 OK \\dATDT\\T TIMEOUT 40 CONNECT"
22 set timeout 180 # 3 minute idle timer (the default)
36 add default HISADDR # Add a (sticky) default route
43 add default HISADDR # Add a (sticky) default route
H A Dppp.831 .Nd Point to Point Protocol (a.k.a. user-ppp)
99 .Bl -tag -width XXX -offset XXX
109 is trying to bring the link up will remain queued for a default of
129 .Pa /usr/share/examples/ppp/ppp.conf.sample
141 exits with a non-zero result.
161 .Dq force-scripts
176 As pipes are not bi-directional, ppp will redirect all writes to descriptor
186 .Dq force-scripts
195 This is a no-op, and gives the same behaviour as if none of the above
208 .Dq default
[all …]
H A DREADME.changes36 o LQR is disabled by default.
37 o Openmode is active by default.
42 o No diagnostic socket is created by default. The `set server' command
46 o When `set server' is used to re-select a diagnostic port, all existing
48 o pppd-deflate is now called deflate24.
49 o Filter IPs of 0.0.0.0 have a default width of 0, not 32.
54 o The default `device' is cuau1, then cuau0
58 utmp host field in -direct mode.
59 o Out-of-sequence FSM packets (IPCP/LCP/CCP) are dropped by default.
61 o ^C works on the parent in -background mode.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DSampleProfile.cpp1 //===- SampleProfile.cpp - Incorporate sample profiles into the IR --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // reads a profile file generated by a sampling profiler (e.g. Linux Perf -
16 // - prof: Represents branch weights. This annotation is added to branches
22 //===----------------------------------------------------------------------===//
99 #define DEBUG_TYPE "sample-profile"
100 #define CSINLINE_DEBUG DEBUG_TYPE "-inline"
123 "sample-profile-file", cl::init(""), cl::value_desc("filename"),
124 cl::desc("Profile file loaded by -sample-profile"), cl::Hidden);
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3368-lion-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3368-lion.dtsi"
10 model = "Theobroma Systems RK3368-uQ7 Baseboard";
11 compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
18 stdout-path = "serial0:115200n8";
32 pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>;
34 sd_card_led: led-3 {
37 linux,default-trigger = "mmc0";
41 dc_12v: dc-12v {
[all …]
H A Drk3368-px5-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
12 compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
20 stdout-path = "serial4:115200n8";
28 keys: gpio-keys {
29 compatible = "gpio-keys";
30 pinctrl-names = "default";
31 pinctrl-0 = <&pwr_key>;
33 key-power {
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/ProfileData/
H A DSampleProfWriter.h1 //===- SampleProfWriter.h - Write LLVM sample profile data ------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains definitions needed for writing sample profiles.
11 //===----------------------------------------------------------------------===//
32 // context information. When Thinlto is enabled, ThinLTO postlink phase only
55 virtual ~FunctionPruningStrategy() = default;
75 /// In this default implementation, functions with fewest samples are dropped
80 /// Empirically, functions with larger total sample count contain linearly
81 /// more sample entries, meaning it takes linearly more space to write them.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSampleProfileInference.cpp1 //===- SampleProfileInference.cpp - Adjust sample profiles in the IR ------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
26 #define DEBUG_TYPE "sample-profile-inference"
31 "sample-profile-even-flow-distribution", cl::init(true), cl::Hidden,
36 "sample-profile-rebalance-unknown", cl::init(true), cl::Hidden,
37 cl::desc("Evenly re-distribute flow among unknown subgraphs."));
40 "sample-profile-join-islands", cl::init(true), cl::Hidden,
44 "sample-profile-profi-cost-block-inc", cl::init(10), cl::Hidden,
[all …]
/freebsd/share/man/man8/
H A Ddiskless.81 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
42 re-installing file systems on a local disk.
48 .Bl -enum
50 The stage-1 bootstrap, typically PXE built into your Ethernet
51 card, loads a second-stage boot program.
53 The second-stage boot program, typically
65 First, the stage-1 bootstrap loads the stage-2 boot program over
67 The stage-1 bootstrap typically uses
83 The stage-2 boot program then loads additional modules and the kernel.
[all …]
/freebsd/share/examples/ppp/
H A Dppp.conf.sample3 # PPP Sample Configuration File
22 # Default setup. Always executed when PPP is invoked.
23 # This section is *not* pre-loaded by the ``load'' or ``dial'' commands.
29 default:
30 set log Phase Chat LCP IPCP CCP tun command
34 OK-AT-OK ATE1Q0 OK \\dATDT\\T TIMEOUT 40 CONNECT"
41 # is required by the server either using a unix-style login procedure
46 # use a unix-style login script:
61 # This entry also works with static IP numbers or when not in -auto mode.
62 # The ``add'' line adds a `sticky' default route that will be updated if
[all …]

1234