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/linux/include/linux/
H A Dkvm_irqfd.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * level triggered interrupts. The interrupt is asserted on eventfd
18 * interrupt is de-asserted and userspace is notified through the
19 * resamplefd. All resamplers on the same gsi are de-asserted
27 * RCU list modified under kvm->irqfds.resampler_lock
32 * Entry in list of kvm->irqfd.resampler_list. Use for sharing
34 * RCU list modified under kvm->irqfds.resampler_lock
40 /* Used for MSI fast-path */
46 /* Used for level IRQ fast-path */
49 /* The resampler used by this irqfd (resampler-only) */
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/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
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/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
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/linux/drivers/video/backlight/
H A Dlms283gf05.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * lms283gf05.c -- support for Samsung LMS283GF05 LCD
95 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
97 gpiod_set_value(gpiod, 1); /* Asserted */ in lms283gf05_reset()
99 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
127 struct spi_device *spi = st->spi; in lms283gf05_power_set()
130 if (st->reset) in lms283gf05_power_set()
131 lms283gf05_reset(st->reset); in lms283gf05_power_set()
135 if (st->reset) in lms283gf05_power_set()
136 gpiod_set_value(st->reset, 1); /* Asserted */ in lms283gf05_power_set()
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/linux/arch/arm/mach-omap2/
H A Dprminst44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
95 * Returns 1 if the (sub)module hardreset line is currently asserted,
96 * 0 if the (sub)module hardreset line is not currently asserted, or
97 * -EINVAL upon parameter error.
112 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
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H A Dprm2xxx_3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
29 * Returns 1 if the (sub)module hardreset line is currently asserted,
30 * 0 if the (sub)module hardreset line is not currently asserted, or
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
47 * reset line to be asserted / deasserted in order to fully enable the
48 * IP. These modules may have multiple hard-reset lines that reset
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H A Dprm33xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
17 #include "prm-regbits-33xx.h"
31 /* Read-modify-write a register in PRM. Caller must lock */
45 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
52 * Returns 1 if the (sub)module hardreset line is currently asserted,
53 * 0 if the (sub)module hardreset line is not currently asserted, or
54 * -EINVAL upon parameter error.
69 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
76 * reset line to be asserted / deasserted in order to fully enable the
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/linux/Documentation/devicetree/bindings/bus/
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
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/linux/include/sound/
H A Dcs4271.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * line is de-asserted. That also means that clocks cannot be changed
18 * a complete re-initialization of all registers.
20 * One (undocumented) workaround is to assert and de-assert the PDN bit
/linux/Documentation/devicetree/bindings/spi/
H A Dcdns,qspi-nor-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
22 cdns,tshsl-ns:
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/linux/Documentation/hwmon/
H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
41 from Jean Delvare <jdelvare@suse.de>
44 ---------
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H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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/linux/drivers/tty/serial/8250/
H A D8250_dwlib.c1 // SPDX-License-Identifier: GPL-2.0+
79 struct dw8250_port_data *d = p->private_data; in dw8250_get_divisor()
81 quot = p->uartclk / base_baud; in dw8250_get_divisor()
82 rem = p->uartclk % base_baud; in dw8250_get_divisor()
83 *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); in dw8250_get_divisor()
98 p->status &= ~UPSTAT_AUTOCTS; in dw8250_do_set_termios()
99 if (termios->c_cflag & CRTSCTS) in dw8250_do_set_termios()
100 p->status |= UPSTAT_AUTOCTS; in dw8250_do_set_termios()
105 p->ignore_status_mask |= DW_UART_LSR_ADDR_RCVD; in dw8250_do_set_termios()
106 p->read_status_mask |= DW_UART_LSR_ADDR_RCVD; in dw8250_do_set_termios()
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/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
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/linux/Documentation/devicetree/bindings/reset/
H A Dti,tps380x-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/ti,tps380x-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
16 reset input (MR). The RESET output remains asserted for the factory
25 - ti,tps3801
27 reset-gpios:
31 "#reset-cells":
35 - compatible
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/linux/Documentation/admin-guide/media/
H A Dbttv.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------------------
12 ./scripts/config -e PCI
13 ./scripts/config -m I2C
14 ./scripts/config -m INPUT
15 ./scripts/config -m MEDIA_SUPPORT
16 ./scripts/config -e MEDIA_PCI_SUPPORT
17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
19 ./scripts/config -e MEDIA_RADIO_SUPPORT
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/linux/drivers/reset/
H A Dreset-simple.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include <linux/reset-controller.h>
21 #include <linux/reset/reset-simple.h>
40 spin_lock_irqsave(&data->lock, flags); in reset_simple_update()
42 reg = readl(data->membase + (bank * reg_width)); in reset_simple_update()
43 if (assert ^ data->active_low) in reset_simple_update()
47 writel(reg, data->membase + (bank * reg_width)); in reset_simple_update()
49 spin_unlock_irqrestore(&data->lock, flags); in reset_simple_update()
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H A Dreset-ti-syscon.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/reset/ti-syscon.h>
20 * struct ti_syscon_reset_control - reset control structure
27 * @flags: reset flag indicating how the (de)assert and status are handled
40 * struct ti_syscon_reset_data - reset controller information structure
42 * @regmap: regmap handle containing the memory-mapped reset registers
57 * ti_syscon_reset_assert() - assert device reset
59 * @id: ID of the reset to be asserted
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #include <linux/reset-controller.h>
39 * struct reset_control - a reset control
71 * struct reset_control_array - an array of reset controls
83 * struct reset_gpio_lookup - lookup key for ad-hoc created reset-gpio devices
98 if (rcdev->dev) in rcdev_name()
99 return dev_name(rcdev->dev); in rcdev_name()
101 if (rcdev->fwnode) in rcdev_name()
102 return fwnode_get_name(rcdev->fwnode); in rcdev_name()
108 * fwnode_reset_simple_xlate - translate reset_spec to the reset line number
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/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80-de.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
7 #include <linux/clk-provider.h>
17 #include "ccu-sun9i-a80-de.h"
19 static SUNXI_CCU_GATE(fe0_clk, "fe0", "fe0-div",
21 static SUNXI_CCU_GATE(fe1_clk, "fe1", "fe1-div",
23 static SUNXI_CCU_GATE(fe2_clk, "fe2", "fe2-div",
25 static SUNXI_CCU_GATE(iep_deu0_clk, "iep-deu0", "de",
27 static SUNXI_CCU_GATE(iep_deu1_clk, "iep-deu1", "de",
29 static SUNXI_CCU_GATE(be0_clk, "be0", "be0-div",
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H A Dccu-sun8i-de2.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
19 #include "ccu-sun8i-de2.h"
21 static SUNXI_CCU_GATE(bus_mixer0_clk, "bus-mixer0", "bus-de",
23 static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de",
25 static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de",
27 static SUNXI_CCU_GATE(bus_rot_clk, "bus-rot", "bus-de",
30 static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div",
32 static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div",
34 static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
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/linux/drivers/pcmcia/
H A Ddb1xxx_ss.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * The Db1000 is used as a reference: Per-socket card-, carddetect- and
15 * bits arranged in per-socket groups in an external PLD. All boards
19 * - Pb1100/Pb1500: single socket only; voltage key bits VS are
21 * - Au1200-based: additional card-eject irqs, irqs not gpios!
22 * - Db1300: Db1200-like, no pwr ctrl, single socket (#1).
37 #include <asm/mach-au1x00/au1000.h>
38 #include <asm/mach-db1x00/bcsr.h>
57 int stschg_irq; /* card-status-change irq */
82 return sigstat & 1 << (8 + 2 * sock->nr); in db1200_card_inserted()
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/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/linux/drivers/cpufreq/
H A Dgx-suspmod.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (C) 2002 Hiroshi Miura <miura@da-cha.org>
10 * software is provided AS-IS with no warranties.
19 * Suspend Modulation works by asserting and de-asserting the SUSP# pin
22 * asserted then power consumption is reduced.
28 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
35 * F_eff = Fgx * ----------------------
43 * on_duration = off_duration * (stock_freq - freq) / freq
46 * on_duration = DURATION - off_duration
48 *---------------------------------------------------------------------------
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