Searched full:ddr52 (Results 1 – 7 of 7) sorted by relevance
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sprd,sdhci-r11.yaml | 53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":
107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;
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| H A D | mmc-controller-common.yaml | 358 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
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| /linux/drivers/mmc/host/ |
| H A D | sdhci_am654.c | 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
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| H A D | dw_mmc-rockchip.c | 197 * DDR52 8-bit mode. in dw_mci_rk3288_set_ios()
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| H A D | sdhci-sprd.c | 110 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
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| H A D | sunxi-mmc.c | 782 * We currently only support the standard MMC DDR52 mode. in sunxi_mmc_clk_set_rate()
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| /linux/drivers/mmc/core/ |
| H A D | host.c | 247 mmc_of_parse_timing_phase(dev, "clk-phase-mmc-ddr52", in mmc_of_parse_clk_phase()
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