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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dfsl,dcu.txt1 Device Tree bindings for Freescale DCU DRM Driver
5 * "fsl,ls1021a-dcu".
6 * "fsl,vf610-dcu".
8 - reg: Address and length of the register set for dcu.
9 - clocks: Handle to "dcu" and "pix" clock (in the order below)
12 - clock-names: Should be "dcu" and "pix"
14 - big-endian Boolean property, LS1021A DCU registers are big-endian.
21 dcu: dcu@2ce0000 {
22 compatible = "fsl,ls1021a-dcu";
25 clock-names = "dcu", "pix";
H A Dfsl,ls1021a-dcu.yaml4 $id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml#
7 title: Freescale DCU DRM Driver
15 - fsl,ls1021a-dcu
16 - fsl,vf610-dcu
29 - const: dcu
59 compatible = "fsl,ls1021a-dcu";
62 clock-names = "dcu", "pix";
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h48 #define AR5311_QDCLKGATE 0x005c /* QCU/DCU clock gating control */
148 #define AR_D0_LCL_IFS 0x1040 /* DCU-specific IFS settings */
149 #define AR_D1_LCL_IFS 0x1044 /* DCU-specific IFS settings */
150 #define AR_D2_LCL_IFS 0x1048 /* DCU-specific IFS settings */
151 #define AR_D3_LCL_IFS 0x104c /* DCU-specific IFS settings */
152 #define AR_D4_LCL_IFS 0x1050 /* DCU-specific IFS settings */
153 #define AR_D5_LCL_IFS 0x1054 /* DCU-specific IFS settings */
154 #define AR_D6_LCL_IFS 0x1058 /* DCU-specific IFS settings */
155 #define AR_D7_LCL_IFS 0x105c /* DCU-specific IFS settings */
156 #define AR_D8_LCL_IFS 0x1060 /* DCU-specific IFS settings */
[all …]
H A Dar5211.h32 /* DCU Transmit Filter macros */
33 #define CALC_MMR(dcu, idx) \ argument
34 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
37 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) argument
H A Dar5211_xmit.c109 * Allocate and initialize a tx DCU/QCU combination.
195 * Free a tx DCU/QCU combination.
284 /* Configure DCU to use the global sequence count */ in ar5211ResetTxQueue()
332 /* Configure DCU for beacons */ in ar5211ResetTxQueue()
352 /* Configure DCU for CAB */ in ar5211ResetTxQueue()
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h45 /* 0x5c is for QCU/DCU clock gating control on 5311 */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
170 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
171 #define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */
172 #define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */
173 #define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */
174 #define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */
175 #define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */
176 #define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */
177 #define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */
[all …]
H A Dar5311reg.h25 #define AR5311_QDCLKGATE 0x005c /* MAC QCU/DCU clock gating control */
27 #define AR5311_QDCLKGATE_DCU_M 0x07FF0000 /* DCU clock disable */
43 * On Maui2/Spirit the frame sequence number is controlled per DCU.
H A Dar5212.h26 /* DCU Transmit Filter macros */
27 #define CALC_MMR(dcu, idx) \ argument
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
31 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) argument
H A Dar5212_xmit.c117 * Allocate and initialize a tx DCU/QCU combination.
227 * Free a tx DCU/QCU combination.
323 /* NB: always enable DCU to wait for next fragment from QCU */ in ar5212ResetTxQueue()
328 /* Configure DCU to use the global sequence count */ in ar5212ResetTxQueue()
/freebsd/lib/libpmc/pmu-events/arch/x86/silvermont/
H A Dcache.json352 …"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response t…
363 "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.",
374 …"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the sno…
385 …"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoo…
396 …"BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding…
407 "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.",
418 "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.",
429 …"BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where m…
440 …"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibli…
451 …"BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss respo…
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A Ddpu.json21 "PublicDescription": "Memory error (any type) from DCU",
24 "BriefDescription": "Memory error (any type) from DCU"
/freebsd/share/man/man4/
H A Duplcom.4163 Sony Ericsson DCU-10 and DCU-11 (Susteen) USB Cables
/freebsd/tools/tools/ath/common/
H A Ddumpregs.h57 DUMP_DCU = 0x0040, /* DCU state */
59 DUMP_PUBLIC = 0x0061, /* public = BASIC+QCU+DCU */
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h523 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control
547 * MAC DCU Registers
552 #define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility
570 /* DCU transmit filter cmd (w/only) */
572 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) // DCU transmit filter data
575 /* MAC DCU-global IFS settings: SIFS duration */
580 /* MAC DCU-global IFS settings: slot duration */
596 /* MAC DCU-global IFS settings: EIFS duration */
609 /* MAC DCU-global IFS settings: Miscellaneous */
613 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a-tqmls1021a-mbls1021a-hdmi.dtso12 &dcu {
H A Dls1021a-tqmls1021a-mbls1021a-lvds-tm070jvhg33.dtso18 &dcu {
H A Dls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso19 &dcu {
H A Dls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso19 &dcu {
H A Dls1021a.dtsi666 dcu: dcu@2ce0000 { label
667 compatible = "fsl,ls1021a-dcu";
672 clock-names = "dcu", "pix";
H A Dls1021a-iot.dts81 &dcu {
/freebsd/lib/libpmc/
H A Dpmc.sandybridge.395 Counts the number of demand and DCU prefetch data reads of full and partial
99 Counts the number of demand and DCU prefetch reads for ownership (RFO)
103 Counts the number of demand and DCU prefetch instruction cacheline reads.
215 Number of cases where any load is blocked but has no DCU miss.
H A Dpmc.haswellxeon.393 Counts the number of demand and DCU prefetch data reads of full
98 Counts the number of demand and DCU prefetch reads for ownership (RFO)
102 Counts the number of demand and DCU prefetch instruction cacheline reads.
H A Dpmc.haswell.392 Counts the number of demand and DCU prefetch data reads of full
97 Counts the number of demand and DCU prefetch reads for ownership (RFO)
101 Counts the number of demand and DCU prefetch instruction cacheline reads.
H A Dpmc.ivybridge.391 Counts the number of demand and DCU prefetch data reads of full and partial
95 Counts the number of demand and DCU prefetch reads for ownership (RFO)
99 Counts the number of demand and DCU prefetch instruction cacheline reads.
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvfxxx.dtsi395 dcu0: dcu@40058000 {
396 compatible = "fsl,vf610-dcu";
401 clock-names = "dcu", "pix";

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