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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g087.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
[all …]
H A Dr9a09g077.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
[all …]
H A Dr9a09g056.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
31 #address-cells = <2>;
32 #size-cells = <2>;
33 interrupt-parent = <&gic>;
35 audio_extal_clk: audio-clk {
36 compatible = "fixed-clock";
[all …]
H A Dr9a09g047.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
[all …]
H A Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
[all …]
H A Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
24 default-brightness-level = <100>;
[all …]
H A Dimx8mp-toradex-smarc.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/phy/phy-imx8-pcie.h>
5 #include <dt-bindings/net/ti-dp83867.h>
26 stdout-path = &uart4;
30 compatible = "gpio-usb-b-connector", "usb-b-connector";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usb0_id>;
33 id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
35 self-powered;
37 vbus-supply = <&reg_usb0_vbus>;
[all …]
H A Dimx8mp-verdin.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h>
12 stdout-path = &uart3;
24 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4>;
28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
H A Dqcs8300-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "monaco-pmics.dtsi"
15 compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
16 chassis-type = "embedded";
24 stdout-path = "serial0:115200n8";
27 regulator-usb2-vbus {
28 compatible = "regulator-fixed";
[all …]
H A Dmonaco-evk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/sound/qcom,q6afe.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "monaco-pmics.dtsi"
17 compatible = "qcom,monaco-evk", "qcom,qcs8300";
26 stdout-path = "serial0:115200n8";
29 dmic: audio-codec-0 {
30 compatible = "dmic-codec";
[all …]
H A Dlemans-evk.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved.
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 #include "lemans-pmics.dtsi"
18 compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p";
26 dmic: audio-codec-0 {
[all …]
H A Dsa8155p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
24 stdout-path = "serial0:115200n8";
27 vreg_3p3: vreg-3p3-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_3p3";
30 regulator-min-microvolt = <3300000>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_dcb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013-2014 Chelsio Communications. All rights reserved.
56 if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
65 CXGB4_DCB_STATE_HOST, /* we're using Host DCB (if at all) */
66 CXGB4_DCB_STATE_FW_INCOMPLETE, /* using firmware DCB, incomplete */
67 CXGB4_DCB_STATE_FW_ALLSYNCED, /* using firmware DCB, all sync'ed */
75 CXGB4_DCB_INPUT_FW_DISABLED, /* firmware DCB disabled */
76 CXGB4_DCB_INPUT_FW_ENABLED, /* firmware DCB enabled */
77 CXGB4_DCB_INPUT_FW_INCOMPLETE, /* firmware reports incomplete DCB */
82 /* Firmware DCB messages that we've received so far ...
[all …]
H A Dcxgb4_debugfs.c4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
57 pos -= tb->skip_first; in seq_tab_get_idx()
58 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width]; in seq_tab_get_idx()
63 struct seq_tab *tb = seq->private; in seq_tab_start()
65 if (tb->skip_first && *pos == 0) in seq_tab_start()
73 v = seq_tab_get_idx(seq->private, *pos + 1); in seq_tab_next()
84 const struct seq_tab *tb = seq->private; in seq_tab_show()
86 return tb->show(seq, v, ((char *)v - tb->data) / tb->width); in seq_tab_show()
[all …]
/linux/include/uapi/linux/
H A Ddcbnl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 2008-2011, Intel Corporation.
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
38 * @cbs: credit based shaper ets algorithm supported
50 * ----
53 * 1 credit-based shaper
55 * 3-254 reserved
94 * given in u-seconds
109 * value is given as percentage (1-100)
114 * the QCN capable hardware may add CN-TAG TLV to the
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
[all …]
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
54 1) Make sure that your system's physical memory is in a high-performance
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-dev.c1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
17 #include "xgbe-common.h"
18 #include "xgbe-sm
[all...]
/linux/drivers/net/ethernet/intel/ice/devlink/
H A Ddevlink.c1 // SPDX-License-Identifier: GPL-2.0
39 put_unaligned_be64(pci_get_dsn(pf->pdev), dsn); in ice_info_get_dsn()
41 snprintf(ctx->buf, sizeof(ctx->buf), "%8phD", dsn); in ice_info_get_dsn()
46 struct ice_hw *hw = &pf->hw; in ice_info_pba()
49 status = ice_read_pba_string(hw, (u8 *)ctx->buf, sizeof(ctx->buf)); in ice_info_pba()
58 struct ice_hw *hw = &pf->h in ice_info_fw_mgmt()
[all...]

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