/linux/drivers/pinctrl/intel/ |
H A D | pinctrl-intel-platform.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2021-2023, Intel Corporation 18 #include "pinctrl-intel.h" 21 struct pinctrl_pin_desc *pins; member 27 struct intel_platform_pins *pins) in intel_platform_pinctrl_prepare_pins() argument 37 descs = devm_krealloc_array(dev, pins->pins, base + size, sizeof(*descs), GFP_KERNEL); in intel_platform_pinctrl_prepare_pins() 39 return -ENOMEM; in intel_platform_pinctrl_prepare_pins() 47 strreplace(pin_name, '-', '_'); in intel_platform_pinctrl_prepare_pins() 50 desc->number = pin_number; in intel_platform_pinctrl_prepare_pins() 51 desc->name = pin_name; in intel_platform_pinctrl_prepare_pins() [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | s3c64xx-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 * - pin control-related definitions 8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are 12 #include "s3c64xx-pinctrl.h" 19 gpa: gpa-gpio-bank { 20 gpio-controller; 21 #gpio-cells = <2>; 22 interrupt-controller; 23 #interrupt-cells = <2>; 26 gpb: gpb-gpio-bank { [all …]
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H A D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source 5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2011-2012 Linaro Ltd. 10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device 14 #include "exynos-pinctrl.h" 17 gpa0: gpa0-gpio-bank { 18 gpio-controller; 19 #gpio-cells = <2>; 21 interrupt-controller; [all …]
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H A D | exynos4x12-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source 8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device 12 #include "exynos-pinctrl.h" 15 pin- ## _pin { \ 16 samsung,pins = #_pin; \ 17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \ 18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \ 22 gpa0: gpa0-gpio-bank { 23 gpio-controller; [all …]
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H A D | exynos5410-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Exynos5410 SoC pin-mux and pin-config device tree source 9 #include "exynos-pinctrl.h" 12 gpa0: gpa0-gpio-bank { 13 gpio-controller; 14 #gpio-cells = <2>; 16 interrupt-controller; 17 #interrupt-cells = <2>; 20 gpa1: gpa1-gpio-bank { 21 gpio-controller; [all …]
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/linux/drivers/net/ethernet/intel/ice/ |
H A D | ice_dpll.c | 1 // SPDX-License-Identifier: GPL-2.0 53 * enum ice_dpll_pin_type - enumerate ice pin types: 58 * @ICE_DPLL_PIN_TYPE_SOFTWARE: software controlled SMA/U.FL pins 71 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input", 83 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW 88 * Check if the pin shall be controlled by SW - instead of providing raw access 89 * for pin control. For E810 NIC with dpll there is additional MUX-related logic 90 * between SMA/U.FL pins/connectors and dpll device, best to give user access 92 * functionality rather then separated pins. 95 * * true - pin controlled by SW [all …]
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/linux/arch/arm64/boot/dts/tesla/ |
H A D | fsd-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Tesla Full Self-Driving SoC device tree source 5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2017-2021 Tesla, Inc. 11 #include "fsd-pinctrl.h" 14 gpf0: gpf0-gpio-bank { 15 gpio-controller; 16 #gpio-cells = <2>; 18 interrupt-controller; 19 #interrupt-cells = <2>; [all …]
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/linux/drivers/pinctrl/samsung/ |
H A D | pinctrl-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 // S3C64xx specific support for pinctrl-samsung driver. 7 // Based on pinctrl-exynos.c, please see the file for original copyrights. 24 #include "pinctrl-samsung.h" 100 #define PIN_BANK_4BIT(pins, reg, id) \ argument 104 .nr_pins = pins, \ 109 #define PIN_BANK_4BIT_EINTG(pins, reg, id, eoffs) \ argument 113 .nr_pins = pins, \ 116 .eint_mask = (1 << (pins)) - 1, \ 121 #define PIN_BANK_4BIT_EINTW(pins, reg, id, eoffs, emask) \ argument [all …]
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/linux/drivers/pinctrl/realtek/ |
H A D | pinctrl-rtd.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 15 #include <linux/pinctrl/pinconf-generic.h> 23 #include "../pinctrl-utils.h" 24 #include "pinctrl-rtd.h" 41 {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0}, 42 {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0}, 43 {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0}, 48 struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); in rtd_pinctrl_get_groups_count() local 50 return data->info->num_groups; in rtd_pinctrl_get_groups_count() 56 struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); in rtd_pinctrl_get_group_name() local [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | qdu1000.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h> 7 #include <dt-bindings/clock/qcom,rpmh.h> 8 #include <dt-bindings/dma/qcom-gpi.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interconnect/qcom,icc.h> 11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/power/qcom-rpmpd.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h> [all …]
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/linux/drivers/pinctrl/vt8500/ |
H A D | pinctrl-wmt.c | 1 // SPDX-License-Identifier: GPL-2.0-only 18 #include <linux/pinctrl/pinconf-generic.h> 24 #include "pinctrl-wmt.h" 26 static inline void wmt_setbits(struct wmt_pinctrl_data *data, u32 reg, in wmt_setbits() argument 31 val = readl_relaxed(data->base + reg); in wmt_setbits() 33 writel_relaxed(val, data->base + reg); in wmt_setbits() 36 static inline void wmt_clearbits(struct wmt_pinctrl_data *data, u32 reg, in wmt_clearbits() argument 41 val = readl_relaxed(data->base + reg); in wmt_clearbits() 43 writel_relaxed(val, data->base + reg); in wmt_clearbits() 75 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); in wmt_pmx_get_function_groups() local [all …]
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/linux/sound/soc/ |
H A D | soc-jack.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 // soc-jack.c -- ALSA SoC jack handling 20 * snd_soc_jack_report - Report the current status for a jack 27 * DAPM pins will be enabled or disabled as appropriate and DAPM 39 if (!jack || !jack->jack) in snd_soc_jack_report() 43 dapm = &jack->card->dapm; in snd_soc_jack_report() 45 mutex_lock(&jack->mutex); in snd_soc_jack_report() 47 jack->status &= ~mask; in snd_soc_jack_report() 48 jack->status |= status & mask; in snd_soc_jack_report() 52 list_for_each_entry(pin, &jack->pins, list) { in snd_soc_jack_report() [all …]
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/linux/drivers/pinctrl/ |
H A D | pinctrl-lantiq.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * linux/drivers/pinctrl/pinctrl-lantiq.c 4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c 17 #include "pinctrl-lantiq.h" 22 return info->num_grps; in ltq_get_group_count() 29 if (selector >= info->num_grps) in ltq_get_group_name() 31 return info->grps[selector].name; in ltq_get_group_name() 36 const unsigned **pins, in ltq_get_group_pins() argument 40 if (selector >= info->num_grps) in ltq_get_group_pins() 41 return -EINVAL; in ltq_get_group_pins() [all …]
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H A D | pinctrl-amdisp.c | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 13 #include "pinctrl-amdisp.h" 15 #define DRV_NAME "amdisp-pinctrl" 28 const struct pinctrl_pin_desc *pins; member 37 .pins = amdisp_pins, 51 const struct amdisp_pinctrl_data *data; member 60 return pctrl->data->ngroups; in amdisp_get_groups_count() 68 return pctrl->data->groups[group].name; in amdisp_get_group_name() 73 const unsigned int **pins, in amdisp_get_group_pins() argument 78 *pins = pctrl->data->groups[group].pins; in amdisp_get_group_pins() [all …]
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/linux/arch/arm/boot/dts/marvell/ |
H A D | kirkwood-nsa320.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk> 9 /dts-v1/; 11 #include "kirkwood-nsa3x0-common.dtsi" 15 compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 24 stdout-path = &uart0; 28 pinctrl: pin-controller@10000 { 29 pinctrl-names = "default"; 31 /* SATA Activity and Present pins are not connected */ 32 pmx_sata0: pmx-sata0 { [all …]
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/linux/Documentation/devicetree/bindings/iio/resolver/ |
H A D | adi,ad2s1210.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter 10 - Michael Hennerich <michael.hennerich@analog.com> 13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking 14 resolver-to-digital converter, integrating an on-board programmable 19 angular velocity data directly from the parallel outputs or through 23 selected by the A0 and A1 input pins. In normal mode, data is latched by 25 data is read or written using a register access scheme (address byte with [all …]
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/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-apq8064-pins.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 sdcc1_default_state: sdcc1-default-state { 5 clk-pins { 6 pins = "sdc1_clk"; 7 drive-strength = <16>; 8 bias-disable; 11 cmd-pins { 12 pins = "sdc1_cmd"; 13 drive-strength = <10>; 14 bias-pull-up; [all …]
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/linux/drivers/auxdisplay/ |
H A D | panel.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright (C) 2000-2008, Willy Tarreau <w@1wt.eu> 5 * Copyright (C) 2016-2017 Glider bvba 10 * The LCD module may either be an HD44780-like 8-bit parallel LCD, or a 1-bit 11 * serial module compatible with Samsung's KS0074. The pins may be connected in 14 * The keypad consists in a matrix of push buttons connecting input pins to 15 * data output pins or to the ground. The combinations have to be hard-coded 22 * - the initialization/deinitialization process is very dirty and should 26 * - document 24 keys keyboard (3 rows of 8 cols, 32 diodes + 2 inputs) 27 * - make the LCD a part of a virtual screen of Vx*Vy [all …]
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/linux/Documentation/driver-api/media/drivers/ |
H A D | bttv-devel.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 ------------------------- 15 bttv-cards.c, which holds the information required for each board. 24 example. The file Documentation/admin-guide/media/bttv-cardlist.rst has a list 48 Below is a do-it-yourself description for you. 50 The bt8xx chips have 32 general purpose pins, and registers to control 51 these pins. One register is the output enable register 52 (``BT848_GPIO_OUT_EN``), it says which pins are actively driven by the 53 bt848 chip. Another one is the data register (``BT848_GPIO_DATA``), where 54 you can get/set the status if these pins. They can be used for input [all …]
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/linux/arch/arm/boot/dts/microchip/ |
H A D | at91sam9x5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC 11 #include <dt-bindings/dma/at91.h> 12 #include <dt-bindings/pinctrl/at91.h> 13 #include <dt-bindings/interrupt-controller/irq.h> 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/clock/at91.h> 16 #include <dt-bindings/mfd/at91-usart.h> 19 #address-cells = <1>; 20 #size-cells = <1>; [all …]
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
H A D | fsl,qe-tsa.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: PowerQUICC QE Time-slot assigner (TSA) controller 10 - Herve Codina <herve.codina@bootlin.com> 13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. 14 Its purpose is to route some TDM time-slots to other internal serial 20 - enum: 21 - fsl,mpc8321-tsa [all …]
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/linux/drivers/pinctrl/nxp/ |
H A D | pinctrl-s32cc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2017-2022,2024 NXP 7 * Copyright 2015-2016 Freescale Semiconductor, Inc. 28 #include "../pinctrl-utils.h" 29 #include "pinctrl-s32.h" 93 * @gpio_configs: Saved configurations for GPIO pins 114 unsigned int mem_regions = ipctl->info->soc_data->mem_regions; in s32_get_region() 118 pin_range = ipctl->regions[i].pin_range; in s32_get_region() 119 if (pin >= pin_range->start && pin <= pin_range->end) in s32_get_region() 120 return &ipctl->regions[i]; in s32_get_region() [all …]
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/linux/drivers/pinctrl/freescale/ |
H A D | pinctrl-imx1-core.c | 1 // SPDX-License-Identifier: GPL-2.0+ 8 // Based on pinctrl-imx.c: 29 #include "pinctrl-imx1.h" 65 * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX 67 * configuration A, input configuration B, GPIO in use and data direction. 70 * bit position and pin id. If they are represented by 2 bit, the lower 16 pins 71 * are in the first register and the upper 16 pins in the second (next) 81 return ipctl->base + port * MX1_PORT_STRIDE; in imx1_mem() 101 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", in imx1_write_2bit() 104 /* Get current state of pins */ in imx1_write_2bit() [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am335x-nano.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/ 5 /dts-v1/; 15 cpu0-supply = <&dcdc2_reg>; 25 compatible = "gpio-leds"; 30 default-state = "off"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&misc_pins>; 39 misc_pins: misc-pins { 40 pinctrl-single,pins = < [all …]
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/linux/drivers/pinctrl/mvebu/ |
H A D | pinctrl-mvebu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 24 #include "pinctrl-mvebu.h" 39 struct mvebu_mpp_ctrl_data *data; member 43 unsigned *pins; member 58 int mvebu_mmio_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data, in mvebu_mmio_mpp_ctrl_get() argument 64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get() 69 int mvebu_mmio_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, in mvebu_mmio_mpp_ctrl_set() argument 76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set() 77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set() [all …]
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