1 /* SPDX-License-Identifier: GPL-2.0+ */
13 #include "pinctrl-amdisp.h"
15 #define DRV_NAME		"amdisp-pinctrl"
28 	const struct pinctrl_pin_desc *pins;  member
37 	.pins = amdisp_pins,
51 	const struct amdisp_pinctrl_data *data;  member
60 	return pctrl->data->ngroups;  in amdisp_get_groups_count()
68 	return pctrl->data->groups[group].name;  in amdisp_get_group_name()
73 				 const unsigned int **pins,  in amdisp_get_group_pins()  argument
78 	*pins = pctrl->data->groups[group].pins;  in amdisp_get_group_pins()
79 	*num_pins = pctrl->data->groups[group].npins;  in amdisp_get_group_pins()
97 	return -EOPNOTSUPP;  in amdisp_gpio_direction_input()
113 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in amdisp_gpio_get()
114 	pin_reg = readl(pctrl->gpiobase + gpio_offset[gpio]);  in amdisp_gpio_get()
115 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in amdisp_gpio_get()
126 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in amdisp_gpio_set()
127 	pin_reg = readl(pctrl->gpiobase + gpio_offset[gpio]);  in amdisp_gpio_set()
132 	writel(pin_reg, pctrl->gpiobase + gpio_offset[gpio]);  in amdisp_gpio_set()
133 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in amdisp_gpio_set()
141 	struct gpio_chip *gc = &pctrl->gc;  in amdisp_gpiochip_add()
142 	struct pinctrl_gpio_range *grange = &pctrl->gpio_range;  in amdisp_gpiochip_add()
145 	gc->label		= dev_name(pctrl->dev);  in amdisp_gpiochip_add()
146 	gc->parent		= &pdev->dev;  in amdisp_gpiochip_add()
147 	gc->names		= amdisp_range_pins_name;  in amdisp_gpiochip_add()
148 	gc->request		= gpiochip_generic_request;  in amdisp_gpiochip_add()
149 	gc->free		= gpiochip_generic_free;  in amdisp_gpiochip_add()
150 	gc->get_direction	= amdisp_gpio_get_direction;  in amdisp_gpiochip_add()
151 	gc->direction_input	= amdisp_gpio_direction_input;  in amdisp_gpiochip_add()
152 	gc->direction_output	= amdisp_gpio_direction_output;  in amdisp_gpiochip_add()
153 	gc->get			= amdisp_gpio_get;  in amdisp_gpiochip_add()
154 	gc->set			= amdisp_gpio_set;  in amdisp_gpiochip_add()
155 	gc->base		= -1;  in amdisp_gpiochip_add()
156 	gc->ngpio		= ARRAY_SIZE(amdisp_range_pins);  in amdisp_gpiochip_add()
158 	grange->id		= 0;  in amdisp_gpiochip_add()
159 	grange->pin_base	= 0;  in amdisp_gpiochip_add()
160 	grange->base		= 0;  in amdisp_gpiochip_add()
161 	grange->pins		= amdisp_range_pins;  in amdisp_gpiochip_add()
162 	grange->npins		= ARRAY_SIZE(amdisp_range_pins);  in amdisp_gpiochip_add()
163 	grange->name		= gc->label;  in amdisp_gpiochip_add()
164 	grange->gc		= gc;  in amdisp_gpiochip_add()
166 	ret = devm_gpiochip_add_data(&pdev->dev, gc, pctrl);  in amdisp_gpiochip_add()
170 	pinctrl_add_gpio_range(pctrl->pctrl, grange);  in amdisp_gpiochip_add()
181 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in amdisp_pinctrl_probe()
183 		return -ENOMEM;  in amdisp_pinctrl_probe()
185 	pdev->dev.init_name = DRV_NAME;  in amdisp_pinctrl_probe()
189 		return -EINVAL;  in amdisp_pinctrl_probe()
191 	pctrl->gpiobase = devm_ioremap_resource(&pdev->dev, res);  in amdisp_pinctrl_probe()
192 	if (IS_ERR(pctrl->gpiobase))  in amdisp_pinctrl_probe()
193 		return PTR_ERR(pctrl->gpiobase);  in amdisp_pinctrl_probe()
197 	pctrl->dev = &pdev->dev;  in amdisp_pinctrl_probe()
198 	pctrl->data = &amdisp_pinctrl_data;  in amdisp_pinctrl_probe()
199 	pctrl->desc.owner = THIS_MODULE;  in amdisp_pinctrl_probe()
200 	pctrl->desc.pctlops = &amdisp_pinctrl_ops;  in amdisp_pinctrl_probe()
201 	pctrl->desc.pmxops = NULL;  in amdisp_pinctrl_probe()
202 	pctrl->desc.name = dev_name(&pdev->dev);  in amdisp_pinctrl_probe()
203 	pctrl->desc.pins = pctrl->data->pins;  in amdisp_pinctrl_probe()
204 	pctrl->desc.npins = pctrl->data->npins;  in amdisp_pinctrl_probe()
205 	ret = devm_pinctrl_register_and_init(&pdev->dev, &pctrl->desc,  in amdisp_pinctrl_probe()
206 					     pctrl, &pctrl->pctrl);  in amdisp_pinctrl_probe()
210 	ret = pinctrl_enable(pctrl->pctrl);  in amdisp_pinctrl_probe()