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Searched +full:d +full:- +full:tlb +full:- +full:sets (Results 1 – 25 of 97) sorted by relevance

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/linux/arch/riscv/boot/dts/sifive/
H A D	fu540-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; [all …]`
H A D	fu740-c000.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 /dts-v1/; 6 #include <dt-bindings/clock/sifive-fu740-prci.h> 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu740-c000", "sifive,fu740"; 23 #address-cells = <1>; 24 #size-cells = <0>; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; [all …]`
/linux/arch/riscv/boot/dts/microchip/
H A D	mpfs.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 8 #address-cells = <2>; 9 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; 21 i-cache-block-size = <64>; [all …]`
/linux/arch/powerpc/boot/dts/
H A D	microwatt.dts	`1 /dts-v1/; 4 #size-cells = <0x02>; 5 #address-cells = <0x02>; 6 model-name = "microwatt"; 7 compatible = "microwatt-soc"; 13 reserved-memory { 14 #size-cells = <0x02>; 15 #address-cells = <0x02>; 26 #clock-cells = <0>; 27 compatible = "fixed-clock"; [all …]`
/linux/arch/arc/mm/
H A D	tlb.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member 26 * Utility Routine to erase a J-TLB entry 63 /* Locate the TLB entry for this vaddr + ASID / in tlb_entry_erase() 82 This also sets up PD0 (vaddr, ASID..) for final commit in tlb_entry_insert() 89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert() 95 /* setup the other half of TLB entry (pfn, rwx..) / in tlb_entry_insert() 101 which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert() [all …]
/linux/arch/riscv/boot/dts/starfive/
H A D	jh7110.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 /dts-v1/; 8 #include <dt-bindings/clock/starfive,jh7110-crg.h> 9 #include <dt-bindings/power/starfive,jh7110-pmu.h> 10 #include <dt-bindings/reset/starfive,jh7110-crg.h> 11 #include <dt-bindings/thermal/thermal.h> 15 #address-cells = <2>; 16 #size-cells = <2>; 19 #address-cells = <1>; 20 #size-cells = <0>; [all …]`
/linux/arch/parisc/include/asm/
H A D	ropes.h	1 /* SPDX-License-Identifier: GPL-2.0 / 5 #include <asm/parisc-device.h> 8 / "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit / 21 * allocated and free'd/purged at a time might make this 33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci / 34 unsigned long imask; / pdir IOV Space mask - shared w/lba_pci / 38 unsigned long res_hint; /* next avail IOVP - circular search / 85 unsigned int num_ioc; / number of on-board IOC's / 98 static inline int IS_ASTRO(struct parisc_device d) { in IS_ASTRO() argument 99 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO() [all …]
/linux/include/asm-generic/
H A D	tlb.h	1 /* SPDX-License-Identifier: GPL-2.0-or-later / 2 / include/asm-generic/tlb.h 4 * Generic TLB shootdown code 32 * Generic MMU-gather implementation. 35 * correct and efficient ordering of freeing pages and TLB invalidation 218 tlb_remove_table(tlb,page) global() argument 279 tlb_delay_rmap(tlb) global() argument 293 tlb_delay_rmap(tlb) global() argument 294 tlb_flush_rmaps(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_flush_rmaps() argument 362 __tlb_adjust_range(struct mmu_gather * tlb,unsigned long address,unsigned int range_size) __tlb_adjust_range() argument 370 __tlb_reset_range(struct mmu_gather * tlb) __tlb_reset_range() argument 404 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 418 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument 437 tlb_update_vma_flags(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_update_vma_flags() argument 455 tlb_flush_mmu_tlbonly(struct mmu_gather * tlb) tlb_flush_mmu_tlbonly() argument 469 tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,int page_size) tlb_remove_page_size() argument 476 __tlb_remove_page(struct mmu_gather * tlb,struct page * page,bool delay_rmap) __tlb_remove_page() argument 486 tlb_remove_page(struct mmu_gather * tlb,struct page * page) tlb_remove_page() argument 491 tlb_remove_ptdesc(struct mmu_gather * tlb,void * pt) tlb_remove_ptdesc() argument 497 tlb_remove_page_ptdesc(struct mmu_gather * tlb,struct ptdesc * pt) tlb_remove_page_ptdesc() argument 502 tlb_change_page_size(struct mmu_gather * tlb,unsigned int page_size) tlb_change_page_size() argument 515 tlb_get_unmap_shift(struct mmu_gather * tlb) tlb_get_unmap_shift() argument 529 tlb_get_unmap_size(struct mmu_gather * tlb) tlb_get_unmap_size() argument 539 tlb_start_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_start_vma() argument 550 tlb_end_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_end_vma() argument 574 tlb_flush_pte_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pte_range() argument 581 tlb_flush_pmd_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pmd_range() argument 588 tlb_flush_pud_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pud_range() argument 595 tlb_flush_p4d_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_p4d_range() argument 603 __tlb_remove_tlb_entry(struct mmu_gather * tlb,pte_t * ptep,unsigned long address) __tlb_remove_tlb_entry() argument 615 tlb_remove_tlb_entry(tlb,ptep,address) global() argument 628 tlb_remove_tlb_entries(struct mmu_gather * tlb,pte_t * ptep,unsigned int nr,unsigned long address) tlb_remove_tlb_entries() argument 641 tlb_remove_huge_tlb_entry(h,tlb,ptep,address) global() argument 660 __tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument 663 tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument 674 __tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument 677 tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument 702 pte_free_tlb(tlb,ptep,address) global() argument 711 pmd_free_tlb(tlb,pmdp,address) global() argument 720 pud_free_tlb(tlb,pudp,address) global() argument 729 p4d_free_tlb(tlb,pudp,address) global() argument [all...]
/linux/arch/mips/mm/
H A D	c-octeon.c	6 * Copyright (C) 2005-2007 Cavium Networks 20 #include <asm/cpu-features.h> 21 #include <asm/cpu-type.h> 33 * Octeon automatically flushes the dcache on tlb changes, so 49 * Flush local I-cache for the specified range. 58 * octeon_flush_icache_all_cores - Flush caches as necessary for all cores 82 mask = mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores() 109 octeon_flush_cache_mm - flush all memory associated with a memory context. 133 * octeon_flush_cache_range - Flush a range out of a vma 142 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range() [all …]
/linux/Documentation/arch/x86/
H A D	pti.rst	1 .. SPDX-License-Identifier: GPL-2.0 27 This approach helps to ensure that side-channel attacks leveraging 30 time. Once enabled at compile-time, it can be disabled at boot with 31 the 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt). 36 When PTI is enabled, the kernel manages two sets of page tables. 43 that any missed kernel->user CR3 switch will immediately crash 49 each CPU's copy of the area a compile-time-fixed virtual address. 65 Protection against side-channel attacks is important. But, 70 a. Each process now needs an order-1 PGD instead of order-0. 89 feature of the MMU allows different processes to share TLB [all …]
H A D	sva.rst	1 .. SPDX-License-Identifier: GPL-2.0 19 application page-faults. For more information please refer to the PCIe 25 mmu_notifier() support to keep the device TLB cache and the CPU cache in 34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits 40 ID (PASID), which is a 20-bit number defined by the PCIe SIG. 43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe 55 ENQCMD works with non-posted semantics and carries a status back if the 67 A new thread-scoped MSR (IA32_PASID) provides the connection between 69 accesses an SVA-capable device, this MSR is initialized with a newly 70 allocated PASID. The driver for the device calls an IOMMU-specific API [all …]
/linux/arch/openrisc/mm/
H A D	tlb.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * OpenRISC tlb.c 11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se> 12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 29 #define NO_CONTEXT -1 35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1)) 36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1)) 38 * Invalidate all TLB entries. 51 /* Determine number of sets for IMMU. / in local_flush_tlb_all() 52 / FIXME: Assumption is I & D nsets equal. */ in local_flush_tlb_all() [all …]
/linux/arch/mips/kvm/
H A D	tlb.c	6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that 7 * TLB handlers run from KSEG0 26 #include <asm/tlb.h> 42 struct mm_struct gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid() 79 clear_root_gid() - Set GuestCtl1.RID for normal root operation. 90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID. 92 * Sets the root GuestID to match the current guest GuestID, for TLB operation 93 * on the GPA->RPA mappings in the root TLB. 96 * possibly longer if TLB registers are modified. 121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv() [all …]
/linux/arch/parisc/include/uapi/asm/
H A D	pdc.h	1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note / 14 #define PDC_BAD_PROC -1 / Called non-existent procedure/ 15 #define PDC_BAD_OPTION -2 / Called with non-existent option / 16 #define PDC_ERROR -3 / Call could not complete without an error / 17 #define PDC_NE_MOD -5 / Module not found / 18 #define PDC_NE_CELL_MOD -7 / Cell module not found / 19 #define PDC_NE_BOOTDEV -9 / Cannot locate a console device or boot device / 20 #define PDC_INVALID_ARG -10 / Called with an invalid argument / 21 #define PDC_BUS_POW_WARN -12 / Call could not complete in allowed power budget / 22 #define PDC_NOT_NARROW -17 / Narrow mode not supported */ [all …]
/linux/arch/parisc/mm/
H A D	fault.c	39 * parisc_acctyp(unsigned int inst) -- 40 * Given a PA-RISC memory access instruction, determine if the 81 * older PA-RISC platforms. The case where a block in parisc_acctyp() 89 * 01 Graphics flush write (IO space -> VM) in parisc_acctyp() 90 * 10 Graphics flush read (VM -> IO space) in parisc_acctyp() 91 * 11 Graphics flush read/write (VM <-> IO space) in parisc_acctyp() 106 * Data TLB miss fault/data page fault in parisc_acctyp() 127 * not, but I want it committed to CVS so I don't lose it :-) 130 if (tree->vm_start > addr) { 131 tree = tree->vm_avl_left; [all …]
/linux/drivers/misc/sgi-gru/
H A D	grufault.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * FAULT HANDLER FOR GRU DETECTED TLB MISSES 7 * This file contains code that handles TLB misses within the GRU. 33 #define VTOP_INVALID -1 34 #define VTOP_RETRY -2 52 vma = vma_lookup(current->mm, vaddr); in gru_find_vma() 53 if (vma && vma->vm_ops == &gru_vm_ops) in gru_find_vma() 62 * - gts with the mmap_lock locked for read and the GTS locked. 63 - NULL if vaddr invalid OR is not a valid GSEG vaddr. 68 struct mm_struct *mm = current->mm; in gru_find_lock_gts() [all …]
/linux/arch/microblaze/include/asm/
H A D	pgtable.h	1 /* SPDX-License-Identifier: GPL-2.0 / 3 Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4 * Copyright (C) 2008-2009 PetaLogix 17 #include <asm-generic/pgtable-nopmd.h> 60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 64 * We use the hash table as an extended TLB, i.e. a cache of currently 65 * active mappings. We maintain a two-level page table tree, much 67 * management code. Low-level assembler code in hashtable.S 74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The 75 * instruction and data sides share a unified, 64-entry, semi-associative [all …]
/linux/arch/sh/kernel/cpu/
H A D	init.c	1 // SPDX-License-Identifier: GPL-2.0 7 * Copyright (C) 2002 - 2009 Paul Mundt 39 * Generic wrapper for command line arguments to disable on-chip 85 * Disable support for slottable sleep instruction, non-nop in expmask_init() 87 * the memory-mapped cache array. in expmask_init() 98 /* 2nd-level cache init / 104 Generic first-level cache init 115 * At this point we don't know whether the cache is enabled or not - a in cache_init() 120 * => before re-initialising the cache, we must do a purge of the whole in cache_init() 123 * - RPC in cache_init() [all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A D	gmc_v7_0.c	74 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers() 127 * gmc_v7_0_init_microcode - load ucode images from disk 142 switch (adev->asic_type) { in gmc_v7_0_init_microcode() 157 return -EINVAL; in gmc_v7_0_init_microcode() 160 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v7_0_init_microcode() 164 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v7_0_init_microcode() 170 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 185 if (!adev->gmc.fw) in gmc_v7_0_mc_load_microcode() 186 return -EINVAL; in gmc_v7_0_mc_load_microcode() 188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v7_0_mc_load_microcode() [all …]
H A D	gmc_v8_0.c	123 switch (adev->asic_type) { in gmc_v8_0_init_golden_registers() 209 * gmc_v8_0_init_microcode - load ucode images from disk 224 switch (adev->asic_type) { in gmc_v8_0_init_microcode() 229 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) \|\| in gmc_v8_0_init_microcode() 230 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) in gmc_v8_0_init_microcode() 236 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) in gmc_v8_0_init_microcode() 242 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { in gmc_v8_0_init_microcode() 259 return -EINVAL; in gmc_v8_0_init_microcode() 262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, in gmc_v8_0_init_microcode() 266 amdgpu_ucode_release(&adev->gmc.fw); in gmc_v8_0_init_microcode() [all …]
/linux/arch/x86/mm/
H A D	pgtable.c	1 // SPDX-License-Identifier: GPL-2.0 6 #include <asm/tlb.h> 11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1; 24 void paravirt_tlb_remove_table(struct mmu_gather tlb, void table) in paravirt_tlb_remove_table() 29 tlb_remove_page(tlb, ptdesc_page(ptdesc)); 33 void paravirt_tlb_remove_table(struct mmu_gather tlb, void table) in pte_alloc_one() 35 tlb_remove_table(tlb, table); 50 return -EINVA in setup_userpte() 23 paravirt_tlb_remove_table(struct mmu_gather * tlb,void * table) paravirt_tlb_remove_table() argument 53 ___pte_free_tlb(struct mmu_gather * tlb,struct page * pte) ___pte_free_tlb() argument 61 ___pmd_free_tlb(struct mmu_gather * tlb,pmd_t * pmd) ___pmd_free_tlb() argument 77 ___pud_free_tlb(struct mmu_gather * tlb,pud_t * pud) ___pud_free_tlb() argument 87 ___p4d_free_tlb(struct mmu_gather * tlb,p4d_t * p4d) ___p4d_free_tlb() argument [all...]
/linux/arch/powerpc/include/asm/book3s/32/
H A D	pgtable.h	1 /* SPDX-License-Identifier: GPL-2.0 / 5 #include <asm-generic/pgtable-nopmd.h> 8 The "classic" 32-bit implementation of the PowerPC MMU uses a hash 12 * We use the hash table as an extended TLB, i.e. a cache of currently 13 * active mappings. We maintain a two-level page table tree, much 15 * management code. Low-level assembler code in hash_low_32.S 27 #define _PAGE_WRITETHRU 0x040 /* W: cache write-through / 53 Location of the PFN in the PTE. Most 32-bit platforms use the same 55 * Platform who don't just pre-define the value so we don't override it here. 60 * The mask covered by the RPN must be a ULL on 32-bit platforms with [all …]
/linux/drivers/iommu/
H A D	exynos-iommu.c	`1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/dma-mapping.h> 25 #include "iommu-pages.h" 40 #define SECT_MASK (~(SECT_SIZE - 1)) 41 #define LPAGE_MASK (~(LPAGE_SIZE - 1)) 42 #define SPAGE_MASK (~(SPAGE_SIZE - 1)) 57 * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces 64 static short PG_ENT_SHIFT = -1; 100 #define section_offs(iova) (iova & (SECT_SIZE - 1)) 102 #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) [all …]`
/linux/mm/
H A D	madvise.c	1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/page-isolation.h> 28 #include <linux/backing-dev.h> 35 #include <asm/tlb.h> 42 * and return -ERESTARTNOINTR to have userspace try again. 47 struct mmu_gather tlb; member 52 Any behaviour which results in changes to the vma->vm_flags needs to 84 /* Add 1 for NUL terminator at the end of the anon_name->name */ in anon_vma_name_alloc() 88 kref_init(&anon_name->kref); in anon_vma_name_alloc() 89 memcpy(anon_name->name, name, count); in anon_vma_name_alloc() [all …]
/linux/arch/x86/kernel/cpu/
H A D	amd.c	1 // SPDX-License-Identifier: GPL-2.0-only 17 #include <asm/spec-ctrl.h> 20 #include <asm/pci-direct.h> 71 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 97 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) / in init_amd_k5() 100 if (c->x86_model == 9 \|\| c->x86_model == 10) { in init_amd_k5() 111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); in init_amd_k6() 113 if (c->x86_model < 6) { in init_amd_k6() 114 / Based on AMD doc 20734R - June 2000 */ in init_amd_k6() 115 if (c->x86_model == 0) { in init_amd_k6() [all …]

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