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/freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.", 6 "BriefDescription": "This event counts the occurrence count of the micro-operation split." 9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A D	GenericCycleImpl.h	1 //===- GenericCycleImpl.h -------------------------------------- C++ ----===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 18 /// - llvm/lib/IR/CycleInfo.cpp 19 /// - llvm/lib/CodeGen/MachineCycleAnalysis.cpp 21 //===----------------------------------------------------------------------===// 30 #define DEBUG_TYPE "generic-cycle-impl" 39 if (Depth > C->Depth) in contains() 41 while (Depth < C->Depth) in contains() 42 C = C->ParentCycle; in contains() [all …]
H A D	GenericUniformityImpl.h	1 //===- GenericUniformityImpl.h ------------------------ C++ -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 17 // - UniformityAnalysis.cpp 23 //===----------------------------------------------------------------------===// 30 /// divergence (whose discovery must be implemented by a CFG- or even 31 /// target-specific derived class), divergence of values is propagated from 32 /// definition to uses in a straight-forward way. The main complexity lies in 42 //===----------------------------------------------------------------------===// 60 /// Construct a specially modified post-order traversal of cycles. [all …]
H A D	GenericCycleInfo.h	1 //===- GenericCycleInfo.h - Info for Cycles in any IR ------- C++ -------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// \brief Find all cycles in a control-flow graph, including irreducible loops. 15 /// - A cycle is a generalization of a loop which can represent 17 /// - Cycles identified in a program are implementation defined, 19 /// - Cycles are well-nested, and form a forest with a parent-child 21 /// - In any choice of DFS, every natural loop L is represented by a 22 /// unique cycle C which is a superset of L. 23 /// - In the absence of irreducible control flow, the cycles are [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	9 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt… 12 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt… 15 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt… 18 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt… 21 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty… 24 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty… 27 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal… 30 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal… 33 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal… 36 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	21 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc… 24 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc… 27 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr… 30 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr… 33 "PublicDescription": "No operation issued due to the frontend, pre-decode error", 36 "BriefDescription": "No operation issued due to the frontend, pre-decode error" 39 …No operation issued due to the backend interlock. This event counts every cycle where the issue of… 42 …No operation issued due to the backend interlock. This event counts every cycle where the issue of… 45 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of… 48 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	floating-point.json	6 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 13 … Each increment represents a one-cycle dispatch event. This event is a speculative event. Since th… 20 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 27 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 34 … Each increment represents a one- cycle dispatch event. This event is a speculative event. Since t… 40 …n": "All FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of e… 46 …-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS. This is a retire-based event. The num… 52 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary … 58 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary … 64 …-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary … [all …]
/freebsd/contrib/bmake/unit-tests/
H A D	dotwait.mk	`5 TESTS= simple recursive shared cycle 11 # Ignore "--- target ---" lines printed by parallel make. 14 @${.MAKE} -f ${THISMAKEFILE} -j4 $t 2>&1 \| grep -v "^--- " 18 # Within each test, the names of the sub-targets follow these 34 PARALLEL_TARG= ${.TARGET:C/\.[a-z]/.*/g:Q} 56 # cycle: the cyclic dependency must not cause infinite recursion 58 cycle: cycle.1.99 .WAIT cycle.2.99 59 cycle.2.99: cycle.2.98 _ECHOUSE 60 cycle.2.98: cycle.2.97 _ECHOUSE 61 cycle.2.97: cycle.2.99 _ECHOUSE`
/freebsd/usr.bin/gprof/
H A D	arcs.c	`1 /- 2 SPDX-License-Identifier: BSD-3-Clause 56 count , parentp -> name , childp -> name ); in addarc() 67 arcp -> arc_count , count ); in addarc() 70 arcp -> arc_count += count; in addarc() 76 arcp -> arc_parentp = parentp; in addarc() 77 arcp -> arc_childp = childp; in addarc() 78 arcp -> arc_count = count; in addarc() 82 arcp -> arc_childlist = parentp -> children; in addarc() 83 parentp -> children = arcp; in addarc() [all …]`
H A D	gprof.callg	`31 its membership in a cycle, if any. 58 parent's membership in a cycle, if any. 84 membership in a cycle, if any. 92 children) in the same cycle as the function. If 93 the function (or child) is a member of a cycle, 96 cycle as a whole. 98 ** static-only parents and children are indicated 103 cycle listings: 104 the cycle as a whole is listed with the same 106 the members of the cycle, and their contributions [all …]`
H A D	gprof.h	1 /- 2 SPDX-License-Identifier: BSD-3-Clause 93 struct arcstruct arc_parentlist; / parents-of-this-child list / 94 struct arcstruct arc_childlist; /* children-of-this-parent list / 95 struct arcstruct arc_next; /* list of arcs on cycle / 127 int toporder; / graph call chain top-sort order / 128 int cycleno; / internal number of cycle on / 130 struct nl cyclehead; /* pointer to head of cycle / 131 struct nl cnext; /* pointer to next member of cycle / 141 #define HASCYCLEXIT 0x08 / node has arc exiting from cycle */ [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A D	floating-point.json	5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.", 6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.", 13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.", 20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.", 27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… 33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.", 34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F… [all …]
/freebsd/share/doc/psd/18.gprof/
H A D	postp.me	88 In these cases, we discover strongly-connected 92 We use a variation of Tarjan's strongly-connected 94 that discovers strongly-connected components as it is assigning 99 For example, a self-recursive routine 100 (a trivial cycle in the call graph) 109 Time is not propagated from one member of a cycle to another, 112 In addition, children of one member of a cycle 113 must be considered children of all members of the cycle. 114 Similarly, parents of one member of the cycle must inherit 115 all members of the cycle as descendants. [all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A D	MachineCycleAnalysis.cpp	1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 29 INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles", 30 "Machine Cycle Info Analysis", true, true) 31 INITIALIZE_PASS_END(MachineCycleInfoWrapperPass, "machine-cycles", 32 "Machine Cycle Info Analysis", true, true) 48 OS << "MachineCycleInfo for function: " << F->getName() << "\n"; in print() 76 INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterPass, "print-machine-cycles", 77 "Print Machine Cycle Info Analysis", true, true) [all …]
H A D	ScoreboardHazardRecognizer.cpp	1 //===- ScoreboardHazardRecognizer.cpp - Scheduler Support -----------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 // encapsultes hazard-avoidance heuristics for scheduling, based on the 13 //===----------------------------------------------------------------------===// 18 #include "llvm/Config/llvm-config.h" 36 // the scoreboard. We always make the scoreboard at least 1 cycle deep to in ScoreboardHazardRecognizer() 39 if (ItinData && !ItinData->isEmpty()) { in ScoreboardHazardRecognizer() 41 if (ItinData->isEndMarker(idx)) in ScoreboardHazardRecognizer() 44 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer() [all …]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A D	pwm-regulator.txt	7 predefined voltage <=> duty-cycle values must be 10 Intermediary duty-cycle values which would normally 13 the user if the assumptions made in continuous-voltage 18 regulator-{min,max}-microvolt properties to calculate 19 appropriate duty-cycle values. This allows for a much 21 voltage-table mode above. This solution does make an 22 assumption that a %50 duty-cycle value will cause the 27 -------------------- 28 - compatible: Should be "pwm-regulator" 30 - pwms: PWM specification (See: ../pwm/pwm.txt) [all …]
H A D	pwm-regulator.yaml	1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Brian Norris <briannorris@chromium.org> 11 - Lee Jones <lee@kernel.org> 12 - Alexandre Courbot <acourbot@nvidia.com> 19 duty-cycle values must be provided via DT. Limitations are that the 21 Intermediary duty-cycle values which would normally allow finer grained 23 is given to the user if the assumptions made in continuous-voltage mode do [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	P9InstrResources.td	1 //===- P9InstrResources.td - P9 Instruction Resource Defs -- tablegen --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 16 // - Each CPU is made up of two superslices. 17 // - Each superslice is made up of two slices. Therefore, there are 4 slices 19 // - Up to 6 instructions can be dispatched to each CPU. Three per superslice. 20 // - Each CPU has: 21 // - One CY (Crypto) unit P9_CY_* 22 // - One DFU (Decimal Floating Point and Quad Precision) unit P9_DFU_* 23 // - Two PM (Permute) units. One on each superslice. P9_PM_* [all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A D	ModuloSchedule.h	1 //===- ModuloSchedule.h - Software pipeline schedule expansion ------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note 19 // that we only support single-block loops, so "block" and "loop" can be used 22 // The Cycle of an instruction defines a partial order of the instructions in 23 // the remapped loop. Instructions within a cycle must not consume the output 24 // of any instruction in the same cycle. Cycle information is assumed to have 26 // lock-step (for example in a VLIW ISA). 52 // an arbitrary schedule containing loop-carried values are complex. [all …]
H A D	MachinePipeliner.h	1 //===- MachinePipeliner.h - Machine Software Pipeliner Pass -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 18 // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa, 22 // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J. 28 // Urbana-Champaign, 2005. 39 //===----------------------------------------------------------------------===// 185 Node2Idx->at(NodeNum) = Idx++; in Circuits() 215 P.MF->getSubtarget().getSMSMutations(Mutations); in SwingSchedulerDAG() 227 int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; } in getASAP() [all …]
/freebsd/sys/contrib/device-tree/Bindings/input/
H A D	pwm-vibrator.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/input/pwm-vibrator.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sebastian Reichel <sre@kernel.org> 14 strength increases based on the duty cycle of the enable PWM channel 15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration). 18 driven at fixed duty cycle. If available this is can be used to increase 23 const: pwm-vibrator 25 pwm-names: [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" 53 "BriefDescription": "Problem-State L1I Directory Writes", [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" 53 "BriefDescription": "Problem-State L1I Directory Writes", [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" 53 "BriefDescription": "Problem-State L1I Directory Writes", [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	basic.json	6 "PublicDescription": "Cycle Count" 18 "PublicDescription": "Level-1 I-Cache Directory Write Count" 24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count" 30 "PublicDescription": "Level-1 D-Cache Directory Write Count" 36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count" 41 "BriefDescription": "Problem-State CPU Cycles", 42 "PublicDescription": "Problem-State Cycle Count" 47 "BriefDescription": "Problem-State Instructions", 48 "PublicDescription": "Problem-State Instruction Count" 53 "BriefDescription": "Problem-State L1I Directory Writes", [all …]

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