| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
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| H A D | apm,xgene-device-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
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| /freebsd/sys/dev/usb/controller/ |
| H A D | musb_otg.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * 2.0 High Speed Dual-Role controller.
87 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
167 .ep_end = -1,
177 ep = td->ep_no; in musbotg_channel_alloc()
180 if (sc->sc_mode == MUSB2_DEVICE_MODE) { in musbotg_channel_alloc()
189 if (sc->sc_channel_mask & (1 << 0)) in musbotg_channel_alloc()
190 return (-1); in musbotg_channel_alloc()
191 sc->sc_channel_mask |= (1 << 0); in musbotg_channel_alloc()
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| /freebsd/sys/dev/qat/qat_hw/qat_c4xxx/ |
| H A D | adf_c4xxx_hw_data.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
132 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
146 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
163 return self ? hweight32(self->accel_mask) : 0; in get_num_accels()
169 return self ? hweight32(self->ae_mask) : 0; in get_num_aes()
198 * c4xxx_set_ssm_wdtimer() - Initialize the slice hang watchdog timer.
206 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in c4xxx_set_ssm_wdtimer()
208 &GET_BARS(accel_dev)[hw_device->get_misc_bar_id(hw_device)]; in c4xxx_set_ssm_wdtimer()
209 struct resource *csr = misc_bar->virt_addr; in c4xxx_set_ssm_wdtimer() local
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| /freebsd/sys/contrib/device-tree/src/arm64/apm/ |
| H A D | apm-storm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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| H A D | apm-shadowcat.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
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| /freebsd/sys/dev/qat/include/common/ |
| H A D | adf_accel_devices.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
64 BIT((vf_nr_)-ADF_VF2PF_SET_SIZE *ADF_VF2PF_VFNR_TO_SET( \
98 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.csr_ops)
99 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.pfvf_ops)
232 * Defines size and offset of compression intermediate buffers stored
233 * in ARAM (device's on-chip memory).
470 /* helper enum for performing CSR operations */
476 /* 32-bit CSR write macro */
480 /* 64-bit CSR write macro */
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| /freebsd/sys/dev/qat/qat_common/ |
| H A D | adf_dev_err.c | 1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
162 sizeof(adf_printf_buf) - adf_printf_len, in adf_print_reg()
175 struct adf_hw_device_data *hw_data = accel_dev->hw_device; in adf_print_err_registers()
177 &GET_BARS(accel_dev)[hw_data->get_misc_bar_id(hw_data)]; in adf_print_err_registers()
178 struct resource *csr = misc_bar->virt_addr; in adf_print_err_registers() local
184 val = ADF_CSR_RD(csr, adf_err_regs[i].offs); in adf_print_err_registers()
192 for (accel = 0, mask = hw_data->accel_mask; mask; in adf_print_err_registers()
196 val = adf_accel_err_regs[i].read(csr, accel); in adf_print_err_registers()
224 struct resource *csr, in adf_handle_slice_hang() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenExtract.cpp | 1 //===- HexagonGenExtract.cpp ----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
33 static cl::opt<unsigned> ExtractCutoff("extract-cutoff", cl::init(~0U),
37 // This prevents generating extract instructions that have the offset of 0.
38 // One of the reasons for "extract" is to put a sequence of bits in a regis-
39 // ter, starting at offset 0 (so that these bits can then be used by an
40 // "insert"). If the bits are already at offset 0, it is better not to gene-
43 static cl::opt<bool> NoSR0("extract-nosr0", cl::init(true), cl::Hidden,
44 cl::desc("No extract instruction with offset 0"));
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineFrameInfo.cpp | 1 //===-- MachineFrameInfo.cpp ---------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
22 #include "llvm/Config/llvm-config.h"
59 int Index = (int)Objects.size() - NumFixedObjects - 1; in CreateStackObject()
69 int Index = (int)Objects.size() - NumFixedObjects - 1; in CreateSpillStackObject()
80 return (int)Objects.size()-NumFixedObjects-1; in CreateVariableSizedObject()
86 // The alignment of the frame index can be determined from its offset from in CreateFixedObject()
87 // the incoming frame position. If the frame object is at offset 32 and in CreateFixedObject()
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| H A D | CFIInstrInserter.cpp | 1 //===------ CFIInstrInserter.cpp - Insert additional CFI instructions -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// blocks. CFA information is information about offset and register set by CFI
15 /// don't. CFI instructions are inserted if basic blocks have incorrect offset
16 /// or register set by previous blocks, as a result of a non-linear layout of
18 //===----------------------------------------------------------------------===//
31 static cl::opt<bool> VerifyCFI("verify-cfiinstrs",
70 /// Value of cfa offset valid at basic block entry.
71 int64_t IncomingCFAOffset = -1;
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| H A D | TargetFrameLoweringImpl.cpp | 1 //===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
41 !MF.getTarget().getMCAsmInfo()->usesWindowsCFI(); in enableCFIFixup()
57 FrameReg = RI->getFrameRegister(MF); in getFrameIndexReference()
59 return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - in getFrameIndexReference()
64 /// Returns the offset from the stack pointer to the slot of the specified
65 /// index. This function serves to provide a comparable offset from a single
66 /// reference point (the value of the stack-pointer at function entry) that can
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jianjun Wang <jianjun.wang@mediatek.com>
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
28 +-+-+-+-+-+-+-+-+
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| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /freebsd/contrib/wpa/src/crypto/ |
| H A D | crypto_wolfssl.c | 3 * Copyright (c) 2004-2017, Jouni Malinen <j@w1.fi>
26 #include <wolfssl/wolfcrypt/error-crypt.h>
165 return -1; in md4_vector()
183 int ret = -1; in md5_vector()
186 return -1; in md5_vector()
191 return -1; in md5_vector()
222 int ret = -1; in sha1_vector()
225 return -1; in sha1_vector()
230 return -1; in sha1_vector()
261 int ret = -1; in sha256_vector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.td | 1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V instructions in TableGen format.
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // RISC-V specific DAG Nodes.
15 //===----------------------------------------------------------------------===//
17 // Target-independent type requirements, but with target-specific formats.
23 // Target-dependent type requirements.
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| /freebsd/sys/dev/iicbus/rtc/ |
| H A D | nxprtc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Driver for NXP real-time clock/calendar chips:
31 * - PCF8563 = low power, countdown timer
32 * - PCA8565 = like PCF8563, automotive temperature range
33 * - PCF8523 = low power, countdown timer, oscillator freq tuning, 2 timers
34 * - PCF2127 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, 512B ram
35 * - PCA2129 = like PCF8523, automotive, tcxo, tamper/ts, i2c & spi, (note 1)
36 * - PCF2129 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, (note 1)
100 * PCF2127-specific registers, bits, and masks.
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| /freebsd/sys/dev/firewire/ |
| H A D | iec13213.h | 1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
63 #define CSRTYPE_C (1 << CSRTYPE_SHIFT) /* CSR offset */
68 * CSR keys
69 * 00 - 2F: defined by CSR architecture standards.
70 * 30 - 37: defined by BUS starndards
71 * 38 - 3F: defined by Vendor/Specifier
238 int offset; member
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| /freebsd/sys/contrib/dev/iwlwifi/ |
| H A D | iwl-csr.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
10 * CSR (control and status registers)
12 * CSR registers are mapped directly into PCI bus space, and are accessible
14 * low power states due to driver-invoked device resets
15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
22 * the CSR registers.
30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
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| /freebsd/sys/arm/ti/ |
| H A D | ti_sdma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
133 #define TI_SDMA_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
134 #define TI_SDMA_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
136 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
138 #define TI_SDMA_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
139 #define TI_SDMA_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
140 #define TI_SDMA_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
149 * ti_sdma_read_4 - reads a 32-bit value from one of the DMA registers
151 * @off: The offset of a register from the DMA register address range
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 1 //===----------------------- SIFrameLowering.cpp --------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //==-----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "frame-info"
24 "amdgpu-spill-vgpr-to-agpr",
46 // callee-save registers since they may appear to be free when this is called
81 unsigned Size = TRI->getSpillSize(RC); in getVGPRSpillLaneOrTempRegister()
82 Align Alignment = TRI->getSpillAlign(RC); in getVGPRSpillLaneOrTempRegister()
97 if (TRI->spillSGPRToVGPR() && in getVGPRSpillLaneOrTempRegister()
98 MFI->allocateSGPRSpillToVGPRLane(MF, FI, /*SpillToPhysVGPRLane=*/true, in getVGPRSpillLaneOrTempRegister()
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| /freebsd/sys/contrib/device-tree/Bindings/serial/ |
| H A D | sirf-uart.txt | 1 * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
6 - reg : Offset and length of the register set for the device
7 - interrupts : Should contain uart interrupt
8 - fifosize : Should define hardware rx/tx fifo size
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
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| /freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
| H A D | dbg-tlv.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2018-2025 Intel Corporation
34 * struct iwl_fw_ini_header - Common Header for all ini debug TLV's structures
46 * struct iwl_fw_ini_addr_size - Base address and size that defines
49 * @addr: the base address (fixed size - 4 bytes)
58 * struct iwl_fw_ini_region_dev_addr_range - Configuration to read
61 * @offset: offset to add to the base address of each chunk
62 * The addrs[] array will be treated as an array of &iwl_fw_ini_addr_size -
66 __le32 offset; member
70 * struct iwl_fw_ini_region_dev_addr - Configuration to read device addresses
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 1 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
35 static const int MaxImmU16 = (1<<16) - 1;
50 int Offset; member
52 StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){}; in StackSlotInfo()
57 return a.Offset < b.Offset; in CompareSSIOffset()
73 int Offset) { in EmitDefCfaOffset() argument
76 MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, Offset)); in EmitDefCfaOffset()
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