Searched +full:cs0 +full:- +full:ground (Results 1 – 6 of 6) sorted by relevance
/linux/Documentation/devicetree/bindings/iio/proximity/ |
H A D | semtech,sx9310.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daniel Campello <campello@chromium.org> 16 https://www.semtech.com/products/smart-sensing/sar-sensors/sx9310 19 - $ref: /schemas/iio/iio.yaml# 24 - semtech,sx9310 25 - semtech,sx9311 37 vdd-supply: 40 svdd-supply: [all …]
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H A D | semtech,sx9324.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Gwendal Grignou <gwendal@chromium.org> 11 - Daniel Campello <campello@chromium.org> 17 - $ref: /schemas/iio/iio.yaml# 32 vdd-supply: 35 svdd-supply: 38 "#io-channel-cells": 41 semtech,ph0-pin: [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sc7180-trogdor-lazor.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "sc7180-trogdor-clamshell.dtsi" 11 semtech,cs0-ground; 12 semtech,combined-sensors = <3>; 14 semtech,startup-sensor = <0>; 15 semtech,proxraw-strength = <8>; 16 semtech,avg-pos-strength = <64>; 34 clock-frequency = <400000>; 37 compatible = "hid-over-i2c"; 39 pinctrl-names = "default"; [all …]
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/linux/drivers/iio/proximity/ |
H A D | sx9310.c | 1 // SPDX-License-Identifier: GPL-2.0 8 * linux-driver-SX9310_NoSmartHSensing>. 132 /* 4 hardware channels, as defined in STAT0: COMB, CS2, CS1 and CS0. */ 168 SX9310_CHANNEL(0), /* CS0 */ 264 ret = regmap_write(data->regmap, SX9310_REG_SENSOR_SEL, chan->channel); in sx9310_read_prox_data() 268 return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val)); in sx9310_read_prox_data() 280 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &val); in sx9310_wait_for_sample() 297 ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL3, ®val); in sx9310_read_gain() 301 switch (chan->channel) { in sx9310_read_gain() 311 return -EINVAL; in sx9310_read_gain() [all …]
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/linux/drivers/spi/ |
H A D | spi-zynq-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0+ 18 #include <linux/spi/spi-mem.h> 28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */ 29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */ 30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */ 31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */ 57 * QSPI Configuration Register - Baud rate and target select 121 * struct zynq_qspi - Defines qspi driver instance 151 return readl_relaxed(xqspi->regs + offset); in zynq_qspi_read() 157 writel_relaxed(val, xqspi->regs + offset); in zynq_qspi_write() [all …]
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/linux/drivers/pinctrl/ |
H A D | pinctrl-gemini.c | 6 * This is a group-only pin controller. 19 #include <linux/pinctrl/pinconf-generic.h> 24 #include "pinctrl-utils.h" 26 #define DRIVER_NAME "pinctrl-gemini" 29 * struct gemini_pin_conf - information about configuring a pin 41 * struct gemini_pmx - state holder for the gemini pin controller 64 * struct gemini_pin_group - describes a Gemini pin group 67 * from the driver-local pin enumeration space 85 /* Some straight-forward control registers */ 98 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot [all …]
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