Lines Matching +full:cs0 +full:- +full:ground
6 * This is a group-only pin controller.
20 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-utils.h"
27 #define DRIVER_NAME "pinctrl-gemini"
30 * struct gemini_pin_conf - information about configuring a pin
42 * struct gemini_pmx - state holder for the gemini pin controller
65 * struct gemini_pin_group - describes a Gemini pin group
68 * from the driver-local pin enumeration space
86 /* Some straight-forward control registers */
99 * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot
102 * - For the bits named *_DISABLE, once you enable something, it cannot be
325 PINCTRL_PIN(163, "K2 IDE CS0 N"),
497 /* Digital ground */
613 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
621 * The parallel flash can be set up in a 26-bit address bus mode exposing
622 * A[0-15] (A[15] takes the place of ALE), but it has the
641 /* The GPIO0B (1-4) pins overlap with TVC and ICE */
644 /* The GPIO0C (5-7) pins overlap with ICE */
650 /* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */
671 /* The GPIO0L (26-29) pins overlap with parallel flash */
677 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
680 /* The GPIO1B (5-10, 27) pins overlap with just IDE */
685 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
691 /* The GPIO1D (28-31) pins overlap with LCD and TVC */
694 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
697 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
700 /* The GPIO2C (8-31) pins overlap with PCI */
1229 PINCTRL_PIN(200, "L1 IDE CS0 N"),
1440 /* Digital ground */
1562 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1570 * The parallel flash can be set up in a 26-bit address bus mode exposing
1571 * A[0-15] (A[15] takes the place of ALE), but it has the
1587 /* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */
1590 /* The GPIO0B (5-7) pins overlap with ICE */
1593 /* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */
1605 /* The GPIO0G (19,20,26-29) pins overlap with parallel flash */
1623 /* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */
1626 /* The GPIO1B (5-10,27) pins overlap with just IDE */
1629 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */
1635 /* The GPIO1D (28-31) pins overlap with TVC */
1638 /* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1641 /* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1644 /* The GPIO2C (8-31) pins overlap with PCI */
1963 if (pmx->is_3512)
1965 if (pmx->is_3516)
1975 if (pmx->is_3512)
1977 if (pmx->is_3516)
1990 if (pmx->flash_pin &&
1991 pmx->is_3512 &&
1997 if (pmx->flash_pin &&
1998 pmx->is_3516 &&
2004 if (pmx->is_3512) {
2008 if (pmx->is_3516) {
2031 * struct gemini_pmx_func - describes Gemini pinmux functions
2204 if (pmx->is_3512)
2206 else if (pmx->is_3516)
2209 dev_err(pmx->dev, "invalid SoC type\n");
2210 return -ENODEV;
2213 dev_dbg(pmx->dev,
2215 func->name, grp->name);
2217 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &before);
2218 regmap_update_bits(pmx->map, GLOBAL_MISC_CTRL,
2219 grp->mask | grp->value,
2220 grp->value);
2221 regmap_read(pmx->map, GLOBAL_MISC_CTRL, &after);
2226 expected = before &= ~grp->mask;
2227 expected |= grp->value;
2231 tmp = grp->mask;
2237 dev_err(pmx->dev,
2242 dev_err(pmx->dev,
2246 dev_dbg(pmx->dev,
2253 tmp = grp->value;
2259 dev_err(pmx->dev,
2264 dev_err(pmx->dev,
2268 dev_dbg(pmx->dev,
2372 for (i = 0; i < pmx->nconfs; i++) {
2373 retconf = &pmx->confs[i];
2374 if (retconf->pin == pin)
2392 return -ENOTSUPP;
2393 regmap_read(pmx->map, conf->reg, &val);
2394 val &= conf->mask;
2395 val >>= (ffs(conf->mask) - 1);
2399 return -ENOTSUPP;
2422 return -EINVAL;
2425 dev_err(pmx->dev,
2427 return -ENOTSUPP;
2429 arg <<= (ffs(conf->mask) - 1);
2430 dev_dbg(pmx->dev,
2432 pin, conf->mask, arg);
2433 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
2436 dev_err(pmx->dev, "Invalid config param %04x\n", param);
2437 return -ENOTSUPP;
2456 if (pmx->is_3512)
2458 if (pmx->is_3516)
2462 if (!grp->driving_mask) {
2463 dev_err(pmx->dev, "pin config group \"%s\" does "
2465 grp->name);
2466 return -EINVAL;
2489 dev_err(pmx->dev,
2492 return -ENOTSUPP;
2494 val <<= (ffs(grp->driving_mask) - 1);
2495 regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
2496 grp->driving_mask,
2498 dev_dbg(pmx->dev,
2500 grp->name, arg, grp->driving_mask, val);
2503 dev_err(pmx->dev, "invalid config param %04x\n", param);
2504 return -ENOTSUPP;
2530 struct device *dev = &pdev->dev;
2538 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
2540 return -ENOMEM;
2542 pmx->dev = &pdev->dev;
2543 parent = dev->parent;
2546 return -ENODEV;
2548 map = syscon_node_to_regmap(parent->of_node);
2553 pmx->map = map;
2564 pmx->is_3512 = true;
2565 pmx->confs = gemini_confs_3512;
2566 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
2571 pmx->is_3516 = true;
2572 pmx->confs = gemini_confs_3516;
2573 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
2579 return -ENODEV;
2597 pmx->flash_pin = !!(val & GLOBAL_STATUS_FLPIN);
2598 dev_info(dev, "flash pin is %s\n", pmx->flash_pin ? "set" : "not set");
2600 pmx->pctl = devm_pinctrl_register(dev, &gemini_pmx_desc, pmx);
2601 if (IS_ERR(pmx->pctl)) {
2603 return PTR_ERR(pmx->pctl);
2612 { .compatible = "cortina,gemini-pinctrl" },