Lines Matching +full:cs0 +full:- +full:ground
1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
57 * QSPI Configuration Register - Baud rate and target select
121 * struct zynq_qspi - Defines qspi driver instance
151 return readl_relaxed(xqspi->regs + offset);
157 writel_relaxed(val, xqspi->regs + offset);
161 * zynq_qspi_init_hw - Initialize the hardware
167 * - Host mode
168 * - Baud rate divisor is set to 2
169 * - Tx threshold set to 1l Rx threshold set to 32
170 * - Flash memory interface mode enabled
171 * - Size of the word to be transferred as 8 bit
173 * - Disable and clear all the interrupts
174 * - Enable manual target select
175 * - Enable manual start
176 * - Deselect all the chip select lines
177 * - Set the size of the word to be transferred as 32 bit
178 * - Set the little endian mode of TX FIFO and
179 * - Enable the QSPI controller
234 if (op->addr.nbytes > 3)
241 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
251 if (xqspi->rxbuf) {
252 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);
253 xqspi->rxbuf += size;
256 xqspi->rx_bytes -= size;
257 if (xqspi->rx_bytes < 0)
258 xqspi->rx_bytes = 0;
262 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
273 if (xqspi->txbuf) {
275 memcpy(&data, xqspi->txbuf, size);
276 xqspi->txbuf += size;
281 xqspi->tx_bytes -= size;
282 zynq_qspi_write(xqspi, offset[size - 1], data);
286 * zynq_qspi_chipselect - Select or deselect the chip select line
292 struct spi_controller *ctlr = spi->controller;
296 /* Select the lower (CS0) or upper (CS1) memory */
297 if (ctlr->num_chipselect > 1) {
307 /* Ground the line to assert the CS */
318 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
326 * Return: 0 on success and -EINVAL on invalid input parameter
344 * i.e. 000 - divide by 2
345 * 001 - divide by 4
346 * ----------------
347 * 111 - divide by 256
350 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
351 op->max_freq)
359 if (spi->mode & SPI_CPHA)
361 if (spi->mode & SPI_CPOL)
372 * zynq_qspi_setup_op - Configure the QSPI controller
382 struct spi_controller *ctlr = spi->controller;
386 if (ctlr->busy)
387 return -EBUSY;
389 ret = clk_enable(qspi->refclk);
393 ret = clk_enable(qspi->pclk);
395 clk_disable(qspi->refclk);
406 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
416 len = xqspi->tx_bytes;
432 if (xqspi->txbuf) {
433 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,
434 xqspi->txbuf, count);
435 xqspi->txbuf += count * 4;
438 writel_relaxed(0, xqspi->regs +
442 xqspi->tx_bytes -= count * 4;
446 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
454 len = xqspi->rx_bytes - xqspi->tx_bytes;
458 if (xqspi->rxbuf) {
459 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,
460 xqspi->rxbuf, count);
461 xqspi->rxbuf += count * 4;
464 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);
466 xqspi->rx_bytes -= count * 4;
467 len -= count * 4;
474 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
503 if (xqspi->tx_bytes) {
512 if (!xqspi->rx_bytes) {
516 complete(&xqspi->data_completion);
526 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
539 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller);
543 zynq_qspi_chipselect(mem->spi, true);
544 zynq_qspi_config_op(xqspi, mem->spi, op);
546 if (op->cmd.opcode) {
547 reinit_completion(&xqspi->data_completion);
548 xqspi->txbuf = (u8 *)&op->cmd.opcode;
549 xqspi->rxbuf = NULL;
550 xqspi->tx_bytes = op->cmd.nbytes;
551 xqspi->rx_bytes = op->cmd.nbytes;
555 if (!wait_for_completion_timeout(&xqspi->data_completion,
557 err = -ETIMEDOUT;
560 if (op->addr.nbytes) {
561 for (i = 0; i < op->addr.nbytes; i++) {
562 xqspi->txbuf[i] = op->addr.val >>
563 (8 * (op->addr.nbytes - i - 1));
566 reinit_completion(&xqspi->data_completion);
567 xqspi->rxbuf = NULL;
568 xqspi->tx_bytes = op->addr.nbytes;
569 xqspi->rx_bytes = op->addr.nbytes;
573 if (!wait_for_completion_timeout(&xqspi->data_completion,
575 err = -ETIMEDOUT;
578 if (op->dummy.nbytes) {
579 tmpbuf = kmalloc(op->dummy.nbytes, GFP_KERNEL);
581 return -ENOMEM;
583 memset(tmpbuf, 0xff, op->dummy.nbytes);
584 reinit_completion(&xqspi->data_completion);
585 xqspi->txbuf = tmpbuf;
586 xqspi->rxbuf = NULL;
587 xqspi->tx_bytes = op->dummy.nbytes;
588 xqspi->rx_bytes = op->dummy.nbytes;
592 if (!wait_for_completion_timeout(&xqspi->data_completion,
594 err = -ETIMEDOUT;
599 if (op->data.nbytes) {
600 reinit_completion(&xqspi->data_completion);
601 if (op->data.dir == SPI_MEM_DATA_OUT) {
602 xqspi->txbuf = (u8 *)op->data.buf.out;
603 xqspi->tx_bytes = op->data.nbytes;
604 xqspi->rxbuf = NULL;
605 xqspi->rx_bytes = op->data.nbytes;
607 xqspi->txbuf = NULL;
608 xqspi->rxbuf = (u8 *)op->data.buf.in;
609 xqspi->rx_bytes = op->data.nbytes;
610 xqspi->tx_bytes = op->data.nbytes;
616 if (!wait_for_completion_timeout(&xqspi->data_completion,
618 err = -ETIMEDOUT;
620 zynq_qspi_chipselect(mem->spi, false);
635 * zynq_qspi_probe - Probe method for the QSPI driver
646 struct device *dev = &pdev->dev;
647 struct device_node *np = dev->of_node;
651 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi));
653 return -ENOMEM;
656 xqspi->dev = dev;
658 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);
659 if (IS_ERR(xqspi->regs)) {
660 ret = PTR_ERR(xqspi->regs);
664 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
665 if (IS_ERR(xqspi->pclk)) {
666 dev_err(&pdev->dev, "pclk clock not found.\n");
667 ret = PTR_ERR(xqspi->pclk);
671 init_completion(&xqspi->data_completion);
673 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
674 if (IS_ERR(xqspi->refclk)) {
675 dev_err(&pdev->dev, "ref_clk clock not found.\n");
676 ret = PTR_ERR(xqspi->refclk);
680 ret = clk_prepare_enable(xqspi->pclk);
682 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
686 ret = clk_prepare_enable(xqspi->refclk);
688 dev_err(&pdev->dev, "Unable to enable device clock.\n");
692 xqspi->irq = platform_get_irq(pdev, 0);
693 if (xqspi->irq < 0) {
694 ret = xqspi->irq;
697 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,
698 0, pdev->name, xqspi);
700 ret = -ENXIO;
701 dev_err(&pdev->dev, "request_irq failed\n");
705 ret = of_property_read_u32(np, "num-cs",
708 ctlr->num_chipselect = 1;
710 ret = -EINVAL;
711 dev_err(&pdev->dev, "only 2 chip selects are available\n");
714 ctlr->num_chipselect = num_cs;
717 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
719 ctlr->mem_ops = &zynq_qspi_mem_ops;
720 ctlr->mem_caps = &zynq_qspi_mem_caps;
721 ctlr->setup = zynq_qspi_setup_op;
722 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
723 ctlr->dev.of_node = np;
726 zynq_qspi_init_hw(xqspi, ctlr->num_chipselect);
728 ret = devm_spi_register_controller(&pdev->dev, ctlr);
730 dev_err(&pdev->dev, "devm_spi_register_controller failed\n");
737 clk_disable_unprepare(xqspi->refclk);
739 clk_disable_unprepare(xqspi->pclk);
747 * zynq_qspi_remove - Remove method for the QSPI driver
762 clk_disable_unprepare(xqspi->refclk);
763 clk_disable_unprepare(xqspi->pclk);
767 { .compatible = "xlnx,zynq-qspi-1.0", },
774 * zynq_qspi_driver - This structure defines the QSPI platform driver
780 .name = "zynq-qspi",