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/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST Microelectronics SPEAr SPI CS GPIO Controller
10 - Viresh Kumar <vireshk@kernel.org>
23 export the control of this interface as gpio.
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
[all …]
H A Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
31 mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
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/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
45 * - <soc>_nand_: all SoC specific structures/functions
49 #include <linux/dma-mapping.h>
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-drc-compact.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
21 stdout-path = "serial0:115200n8";
25 compatible = "gpio-leds";
29 default-state = "off";
35 default-state = "off";
40 compatible = "regulator-fixed";
41 regulator-name = "vio";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 gpio = <&gpioh 2 GPIO_ACTIVE_LOW>;
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/linux/arch/riscv/boot/dts/canaan/
H A Dsipeed_maix_dock.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w",
18 "canaan,kendryte-k210";
26 stdout-path = "serial0:115200n8";
29 gpio-leds {
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H A Dcanaan_kd233.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
24 stdout-path = "serial0:115200n8";
27 gpio-leds {
28 compatible = "gpio-leds";
39 gpio-keys {
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H A Dsipeed_maix_bit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm",
18 "canaan,kendryte-k210";
26 stdout-path = "serial0:115200n8";
29 gpio-leds {
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H A Dsipeed_maix_go.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-go", "canaan,kendryte-k210";
25 stdout-path = "serial0:115200n8";
28 gpio-leds {
29 compatible = "gpio-leds";
[all …]
H A Dsipeed_maixduino.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "sipeed,maixduino", "canaan,kendryte-k210";
24 stdout-path = "serial0:115200n8";
27 gpio-keys {
28 compatible = "gpio-keys";
30 key-boot {
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
H A Dspi-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
14 dedicated GPIO lines.
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
[all …]
H A Dspi-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 MOSI /--------------------------------+--------+--------+--------\
17 MISO |/------------------------------+|-------+|-------+|-------\|
18 SCL ||/----------------------------+||------+||------+||------\||
20 +------------+ ||| ||| ||| |||
21 | SoC ||| | +-+++-+ +-+++-+ +-+++-+ +-+++-+
23 | +--+++-+ | CS-X +------+\ +--+--+ +--+--+ +--+--+ +--+--+
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/linux/arch/m68k/include/asm/
H A Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
55 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
56 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
58 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
59 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
61 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
62 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
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/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
22 wakeup-source;
25 compatible = "google,cros-ec-pwm";
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dnxp,mc33xs2410.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-side switch MC33XS2410
10 - Dimitri Fedrau <dima.fedrau@gmail.com>
13 - $ref: pwm.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 spi-max-frequency:
26 spi-cpha: true
28 spi-cs-setup-delay-ns:
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/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
7 compatible = "cavium,octeon-3860";
8 #address-cells = <2>;
9 #size-cells = <2>;
10 interrupt-parent = <&ciu>;
13 compatible = "simple-bus";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 ciu: interrupt-controller@1070000000000 {
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d3_eds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
10 /dts-v1/;
15 compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_key_gpio>;
28 button-3 {
[all …]
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
23 gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
[all …]
/linux/drivers/spi/
H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 /*----------------------------------------------------------------------*/
25 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
26 * Use this for GPIO or shift-register level hardware APIs.
28 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
30 * used, though maybe they're called from controller-aware code.
32 * chipselect() and friends may use spi_device->controller_data and
36 * NOTE: SPI controller pins can often be used as GPIO pins instead,
58 unsigned int bits = t->bits_per_word; in bitbang_txrx_8()
59 unsigned int count = t->len; in bitbang_txrx_8()
[all …]
H A Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI host driver using generic bitbanged GPIO
8 #include <linux/gpio/consumer.h>
25 * platform_device->driver_data ... points to spi_gpio
27 * spi->controller_state ... reserved for bitbang framework code
29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
40 /*----------------------------------------------------------------------*/
44 /*----------------------------------------------------------------------*/
52 bang = spi_controller_get_devdata(spi->controller); in spi_to_spi_gpio()
62 gpiod_set_value_cansleep(spi_gpio->sck, is_on); in setsck()
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 pattern: "^nand-controller(@.*)?"
23 "#address-cells":
26 "#size-cells":
31 cs-gpios:
[all …]

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