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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. CPUFREQ
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
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H A Dcpufreq-mediatek-hw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek's CPUFREQ
10 - Hector Yuan <hector.yuan@mediatek.com>
13 CPUFREQ HW is a hardware engine used by MediaTek SoCs to
19 const: mediatek,cpufreq-hw
25 Addresses and sizes for the memory of the HW bases in
29 "#performance-domain-cells":
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H A Dcpufreq-qcom-hw.txt1 Qualcomm Technologies, Inc. CPUFREQ Bindings
3 CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
26 Definition: Addresses and sizes for the memory of the HW bases in
28 - reg-names
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H A Dti-cpufreq.txt1 TI CPUFreq and OPP bindings
6 The ti-cpufreq driver can use revision and an efuse value from the SoC to
8 used to determine which OPPs from the operating-points-v2 table get enabled
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx,
20 - syscon: A phandle pointing to a syscon node representing the control module
24 --------------------
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H A Dcpufreq-st.txt1 Binding for ST's CPUFreq driver
4 ST's CPUFreq driver attempts to read 'process' and 'version' attributes
10 ----------------------
16 - operating-points : [See: ../power/opp-v1.yaml]
19 --------------
24 operating-points = <1500000 0
32 --------------------------------------------
34 This requires the ST CPUFreq driver to supply 'process' and 'version' info.
38 - operating-points-v2 : [See ../power/opp-v2.yaml]
41 ----------------
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H A Dimx-cpufreq-dt.txt1 i.MX CPUFreq-DT OPP bindings
6 the opp-supported-hw values for each OPP to check if the OPP is allowed.
9 --------------------
11 For each opp entry in 'operating-points-v2' table:
12 - opp-supported-hw: Two bitmaps indicating:
13 - Supported speed grade mask
14 - Supported market segment mask
21 --------
24 compatible = "operating-points-v2";
25 opp-1000000000 {
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H A Dnvidia,tegra20-cpufreq.txt1 Binding for NVIDIA Tegra20 CPUFreq
5 - clocks: Must contain an entry for the CPU clock.
6 See ../clocks/clock-bindings.txt for details.
7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details.
8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
10 For each opp entry in 'operating-points-v2' table:
11 - opp-supported-hw: Two bitfields indicating:
23 - opp-microvolt: CPU voltage triplet.
26 - cpu-supply: Phandle to the CPU power supply.
31 regulator-name = "vdd_cpu";
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/freebsd/share/man/man4/
H A Dest.436 .Bd -ragged -offset indent
37 .Cd "device cpufreq"
47 .Xr cpufreq 4
53 .Xr cpufreq 4
61 .Bl -tag -width indent
62 .It hw.est.msr_info
66 .It hw.est.strict
75 .Bl -tag -width indent
94 .Bl -diag
111 .Xr cpufreq 4
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H A Dacpi_thermal.455 .Bl -tag -width indent
56 .It Va hw.acpi.thermal.min_runtime
59 .It Va hw.acpi.thermal.polling_rate
61 .It Va hw.acpi.thermal.user_override
66 .It Va hw.acpi.thermal.tz%d.active
68 If this is non-negative, the appropriate _AC%d object is running.
71 .It Va hw.acpi.thermal.tz%d.passive_cooling
74 .Xr cpufreq 4
77 .It Va hw.acpi.thermal.tz%d.thermal_flags
79 These are bit-masked values.
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/freebsd/contrib/arm-optimized-routines/networking/test/
H A Dchksum.c4 * Copyright (c) 2016-2020, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
35 #define ALIGN(x, y) (((x) + (y) - 1) & ~((y) - 1))
37 /* Reference implementation - do not modify! */
42 uint64_t sum = 0;/* Need 64-bit accumulator when nbytes > 64K */ in checksum_simple()
44 /* Sum all halfwords, assume misaligned accesses are handled in HW */ in checksum_simple()
45 for (uint32_t nhalfs = nbytes >> 1; nhalfs != 0; nhalfs--) in checksum_simple()
56 /* Fold 64-bit sum to 32 bits */ in checksum_simple()
61 /* Fold 32-bit sum to 16 bits */ in checksum_simple()
95 return -1; in find_impl()
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/freebsd/sys/conf/
H A Dfiles.powerpc5 # The long compile-with and dependency lines are required because of
6 # limitations in config: backslash-newline doesn't work in strings, and
14 contrib/openzfs/module/icp/asm-ppc64/blake3/b3_ppc64le_sse2.S optional zfs compile-with "${ZFS_S}"
15 contrib/openzfs/module/icp/asm-ppc64/blake3/b3_ppc64le_sse41.S optional zfs compile-with "${ZFS_S}"
18 contrib/openzfs/module/icp/asm-ppc64/sha2/sha256-p8.S optional zfs compile-with "${ZFS_S}"
19 contrib/openzfs/module/icp/asm-ppc6
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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v
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H A Dqcom-nvmem-cpufreq.txt1 Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
11 to provide the OPP framework with required information (existing HW bitmap).
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
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/freebsd/sys/contrib/device-tree/Bindings/dvfs/
H A Dperformance-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
30 \#performance-domain-cells property in the performance domain provider node.
35 "#performance-domain-cells":
44 performance-domains:
45 $ref: /schemas/types.yaml#/definitions/phandle-array
53 - |
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap36xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/media/omap3-isp.h>
21 operating-points-v2 = <&cpu0_opp_table>;
23 vbb-supply = <&abb_mpu_iva>;
24 clock-latency = <300000>; /* From omap-cpufreq driver */
25 #cooling-cells = <2>;
29 cpu0_opp_table: opp-table {
30 compatible = "operating-points-v2-ti-cpu";
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H A Domap5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 interrupt-parent = <&wakeupgen>;
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H A Dam33xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/am33xx.h>
11 #include <dt-bindings/clock/am3.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
30 d-can0 = &dcan0;
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8996pro.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /delete-node/ opp-table-cluster0;
10 /delete-node/ opp-table-cluster1;
13 * On MSM8996 Pro the cpufreq driver shifts speed bins into the high
14 * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1
18 cluster0_opp: opp-table-cluster0 {
19 compatible = "operating-points-v2-kryo-cpu";
20 nvmem-cells = <&speedbin_efuse>;
21 opp-shared;
23 opp-307200000 {
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H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
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/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_cpufreq.c1 /*-
2 * Copyright (C) 2013-2015 Daisuke Aoyama <aoyama@peach.ne.jp>
71 #define MIN_OVER_VOLTAGE -16
73 #define MSG_ERROR -999999999
85 /* ARM->VC mailbox property semaphore */
115 { "broadcom,bcm2835-vc", 1 },
116 { "broadcom,bcm2708-vc", 1 },
126 TUNABLE_INT("hw.bcm2835.cpufreq.verbose", &cpufreq_verbose);
128 TUNABLE_INT("hw.bcm2835.cpufreq.lowest_freq", &cpufreq_lowest_freq);
176 err = bcm2835_firmware_property(sc->firmware, in bcm2835_cpufreq_get_clock_rate()
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_cpufreq.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
72 {204000000UL, 1007452, -23865, 370},
73 {306000000UL, 1052709, -24875, 370},
74 {408000000UL, 1099069, -25895, 370},
75 {510000000UL, 1146534, -26905, 370},
76 {612000000UL, 1195102, -27915, 370},
77 {714000000UL, 1244773, -28925, 370},
78 {816000000UL, 1295549, -29935, 370},
79 {918000000UL, 1347428, -30955, 370},
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_cpufreq.c1 /*-
73 { 204000000ULL, 1112619, -29295, 402},
74 { 306000000ULL, 1150460, -30585, 402},
75 { 408000000ULL, 1190122, -31865, 402},
76 { 510000000ULL, 1231606, -33155, 402},
77 { 612000000ULL, 1274912, -34435, 402},
78 { 714000000ULL, 1320040, -35725, 402},
79 { 816000000ULL, 1366990, -37005, 402},
80 { 918000000ULL, 1415762, -38295, 402},
81 {1020000000ULL, 1466355, -39575, 402},
[all …]
/freebsd/sys/x86/cpufreq/
H A Dhwpstate_intel.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
51 #include <x86/cpufreq/hwpstate_intel_internal.h>
76 /* cpufreq interface */
114 "Set 1 (default) to enable package-level control, 0 to disable");
127 dev = sc->dev; in intel_hwp_dump_sysctl_handler()
136 sched_bind(curthread, pc->pc_cpuid); in intel_hwp_dump_sysctl_handler()
140 sbuf_printf(sb, "CPU%d: HWP %sabled\n", pc->pc_cpuid, in intel_hwp_dump_sysctl_handler()
156 if (sc->hwp_pkg_ctrl && (data & IA32_HWP_REQUEST_PACKAGE_CONTROL)) in intel_hwp_dump_sysctl_handler()
162 if (!sc->hwp_pkg_ctrl || (data & x) != 0) \ in intel_hwp_dump_sysctl_handler()
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/freebsd/sys/amd64/conf/
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
69 # These controllers have a SCSI-like interface, and require the
113 # EFI pseudo-device
134 # Enable 32-bit runtime support for FreeBSD/i386 binaries.
137 # Enable (32-bit) a.out binary support
/freebsd/sys/i386/conf/
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
61 # CPU_BLUELIGHTNING_3X enables triple-clock mode on IBM Blue Lightning
62 # CPU if CPU supports it. The default is double-clock mode on
76 # mapped mode. Default is 2-way set associative mode.
88 # using group of hw.crusoe.* sysctls.
124 # K5/K6/K6-2 CPUs.
130 # without cache flush at hold state, and (2) write-back CPU cache on
136 # and should be included for any non-Pentium CPU that defines it.
139 # which indicates that the 15-1
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