xref: /freebsd/share/man/man4/est.4 (revision fa9896e082a1046ff4fbc75fcba4d18d1f2efc19)
15486d2ecSSean Bruno.\"
25486d2ecSSean Bruno.\" Copyright (c) 2012 Sean Bruno <sbruno@freebsd.org>
35486d2ecSSean Bruno.\" All rights reserved.
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165486d2ecSSean Bruno.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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26*9157ca0fSLi-Wen Hsu.Dd April 21, 2020
275486d2ecSSean Bruno.Dt EST 4
285486d2ecSSean Bruno.Os
295486d2ecSSean Bruno.Sh NAME
305486d2ecSSean Bruno.Nm est
315486d2ecSSean Bruno.Nd Enhanced Speedstep Technology
325486d2ecSSean Bruno.Sh SYNOPSIS
335486d2ecSSean BrunoTo compile this capability into your kernel
345486d2ecSSean Brunoplace the following line in your kernel
355486d2ecSSean Brunoconfiguration file:
365486d2ecSSean Bruno.Bd -ragged -offset indent
375486d2ecSSean Bruno.Cd "device cpufreq"
385486d2ecSSean Bruno.Ed
395486d2ecSSean Bruno.Sh DESCRIPTION
405486d2ecSSean BrunoThe
415486d2ecSSean Bruno.Nm
425486d2ecSSean Brunointerface provides support for the Intel Enhanced Speedstep Technology.
435486d2ecSSean Bruno.Pp
445486d2ecSSean BrunoNote that
455486d2ecSSean Bruno.Nm
465486d2ecSSean Brunocapabilities are automatically loaded by the
475486d2ecSSean Bruno.Xr cpufreq 4
485486d2ecSSean Brunodriver.
495486d2ecSSean Bruno.Sh LOADER TUNABLES
505486d2ecSSean BrunoThe
515486d2ecSSean Bruno.Nm
525486d2ecSSean Brunointerface is intended to allow
535486d2ecSSean Bruno.Xr cpufreq 4
545486d2ecSSean Brunoto access and implement Intel Enhanced SpeedStep Technology via
555486d2ecSSean Bruno.Xr acpi 4
565486d2ecSSean Brunoand the acpi_perf interface accessors.
575486d2ecSSean BrunoIf the default settings are not optimal, the following sysctls can be
585486d2ecSSean Brunoused to modify or monitor
595486d2ecSSean Bruno.Nm
605486d2ecSSean Brunobehavior.
615486d2ecSSean Bruno.Bl -tag -width indent
625486d2ecSSean Bruno.It hw.est.msr_info
635486d2ecSSean BrunoAttempt to infer information from direct probing of the msr.
6448f219c0SSean BrunoShould only be used in diagnostic cases.
655486d2ecSSean Bruno.Pq default 0
665486d2ecSSean Bruno.It hw.est.strict
67*9157ca0fSLi-Wen HsuValidate frequency requested is accepted by the CPU when set.
68bf7f8bd3SSean BrunoIt appears that this will only work on single core cpus.
695486d2ecSSean Bruno.Pq default 0
705486d2ecSSean Bruno.El
7148f219c0SSean Bruno.Sh SYSCTL VARIABLES
7248f219c0SSean BrunoThe following
7348f219c0SSean Bruno.Xr sysctl 8
7448f219c0SSean Brunovalues are available
7548f219c0SSean Bruno.Bl -tag -width indent
76*9157ca0fSLi-Wen Hsu.It Va dev.est.%d.%desc
7748f219c0SSean BrunoDescription of support, almost always Enhanced SpeedStep Frequency Control.
7848f219c0SSean Bruno.It dev.est.0.%desc: Enhanced SpeedStep Frequency Control
79*9157ca0fSLi-Wen Hsu.It Va dev.est.%d.%driver
8048f219c0SSean BrunoDriver in use, always est.
8148f219c0SSean Bruno.It dev.est.0.%driver: est
82*9157ca0fSLi-Wen Hsu.It Va dev.est.%d.%parent
83*9157ca0fSLi-Wen HsuThe CPU that is exposing these frequencies.
8448f219c0SSean BrunoFor example
8548f219c0SSean Bruno.Va cpu0 .
86*9157ca0fSLi-Wen Hsu.It dev.est.0.%parent: cpu0
8748f219c0SSean Bruno.It Va dev.est.%d.freq_settings .
8848f219c0SSean BrunoThe valid frequencies that are allowed by this CPU and their step values.
8948f219c0SSean Bruno.It dev.est.0.freq_settings: 2201/45000 2200/45000 2000/39581 1900/37387
9048f219c0SSean Bruno1800/34806 1700/32703 1600/30227 1500/28212 1400/25828 1300/23900 1200/21613
9148f219c0SSean Bruno1100/19775 1000/17582 900/15437 800/13723
9248f219c0SSean Bruno.El
935486d2ecSSean Bruno.Sh DIAGNOSTICS
945486d2ecSSean Bruno.Bl -diag
955486d2ecSSean Bruno.It "est%d: <Enhanced SpeedStep Frequency Control> on cpu%d"
965486d2ecSSean Bruno.Pp
975486d2ecSSean BrunoIndicates normal startup of this interface.
985486d2ecSSean Bruno.It "est: CPU supports Enhanced Speedstep, but is not recognized."
995486d2ecSSean Bruno.It "est: cpu_vendor GenuineIntel, msr 471c471c0600471c"
1005486d2ecSSean Bruno.It "device_attach: est%d attach returned 6"
1015486d2ecSSean Bruno.Pp
1025486d2ecSSean BrunoIndicates all attempts to attach to this interface have failed.
1035486d2ecSSean BrunoThis usually indicates an improper BIOS setting restricting O/S
1045486d2ecSSean Brunocontrol of the CPU speeds.
1055486d2ecSSean BrunoConsult your BIOS documentation for more details.
1065486d2ecSSean Bruno.El
1075486d2ecSSean Bruno.Sh COMPATIBILITY
1085486d2ecSSean Bruno.Nm
1095486d2ecSSean Brunois only found on supported Intel CPUs.
1105486d2ecSSean Bruno.Sh SEE ALSO
1115486d2ecSSean Bruno.Xr cpufreq 4
112281858b4SJoel Dahl.Rs
113281858b4SJoel Dahl.%T "Intel 64 and IA-32 Architectures Software Developer Manuals"
114281858b4SJoel Dahl.%U "http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html"
115281858b4SJoel Dahl.Re
1165486d2ecSSean Bruno.Sh AUTHORS
1175486d2ecSSean BrunoThis manual page was written by
1186c899950SBaptiste Daroussin.An Sean Bruno Aq Mt sbruno@FreeBSD.org .
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