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/linux/arch/arm64/boot/dts/sprd/
H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
23 cpu = <&CPU0>;
[all …]
H A Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
21 cpu = <&CPU0>;
24 cpu = <&CPU1>;
27 cpu = <&CPU2>;
[all …]
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
22 "syscon"
[all …]
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
20 Optional properties for the primary CPU node:
21 - enable-method: should be "brcm,bcm63138"
[all …]
/linux/arch/arm/mach-axxia/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-axxia/platsmp.c
15 /* Syscon register offsets for releasing cores from reset */
31 static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle) in axxia_boot_secondary() argument
34 void __iomem *syscon; in axxia_boot_secondary() local
37 syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon"); in axxia_boot_secondary()
39 return -ENOENT; in axxia_boot_secondary()
41 syscon = of_iomap(syscon_np, 0); in axxia_boot_secondary()
43 if (!syscon) in axxia_boot_secondary()
44 return -ENOMEM; in axxia_boot_secondary()
[all …]
/linux/arch/arm64/boot/dts/realtek/
H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/linux/Documentation/devicetree/bindings/soc/microchip/
H A Dmicrochip,sparx5-cpu-syscon.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,sparx5-cpu-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 CPU Syscon
10 - Lars Povlsen <lars.povlsen@microchip.com>
15 - const: microchip,sparx5-cpu-syscon
16 - const: syscon
17 - const: simple-mfd
22 mux-controller:
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
20 cpu@0 {
21 compatible = "arm,cortex-a15";
22 device_type = "cpu";
26 cpu@1 {
[all …]
H A Dkeystone-k2e.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
20 cpu@0 {
21 compatible = "arm,cortex-a15";
22 device_type = "cpu";
26 cpu@1 {
[all …]
/linux/drivers/power/reset/
H A Docelot-reset.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 #include <linux/mfd/syscon.h>
19 const char *syscon; member
48 u32 if_si_owner_bit = ctx->props->if_si_owner_bit; in ocelot_restart_handle()
51 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in ocelot_restart_handle()
52 ctx->props->vcore_protect, 0); in ocelot_restart_handle()
56 regmap_update_bits(ctx->cpu_ctrl, in ocelot_restart_handle()
63 writel(SOFT_CHIP_RST, ctx->base); in ocelot_restart_handle()
72 struct device *dev = &pdev->dev; in ocelot_reset_probe()
75 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in ocelot_reset_probe()
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dmicrochip,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
25 - microchip,lan966x-switch-reset
29 - description: global control block registers
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm7445.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #address-cells = <2>;
6 #size-cells = <2>;
9 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu@0 {
20 compatible = "brcm,brahma-b15";
21 device_type = "cpu";
[all …]
/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
H A Dmt8365.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mediatek,mt8365-power.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux/arch/mips/boot/dts/brcm/
H A Dbcm3368.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm3368-clock.h"
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
14 mips-hpt-frequency = <150000000>;
16 cpu@0 {
18 device_type = "cpu";
22 cpu@1 {
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Drk3368.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
[all …]
H A Dmt7629.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/mt7629-clk.h>
11 #include <dt-bindings/power/mt7622-power.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/reset/mt7629-resets.h>
18 interrupt-parent = <&sysirq>;
19 #address-cells = <1>;
[all …]
/linux/drivers/cpufreq/
H A Dsti-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Match running platform with pre-defined OPP values for CPUFreq
11 #include <linux/cpu.h>
13 #include <linux/mfd/syscon.h>
43 * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
45 * @cpu: CPU's OF node
46 * @syscfg_eng: Engineering Syscon register map
47 * @syscfg: Syscon register map
50 struct device *cpu; member
56 struct device_node *np = ddata.cpu->of_node; in sti_cpufreq_fetch_major()
[all …]
/linux/arch/arm/boot/dts/cirrus/
H A Dep7209.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /dts-v1/;
5 #include <dt-bindings/clock/clps711x-clock.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
28 #address-cells = <0>;
29 #size-cells = <0>;
31 cpu {
32 device_type = "cpu";
38 #address-cells = <1>;
[all …]
/linux/arch/arm/mach-versatile/
H A Dplatsmp-realview.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/mfd/syscon.h>
23 * old RealView EB Cortex-A9 device trees that were using this
26 { .compatible = "arm,arm11mp-scu", },
27 { .compatible = "arm,cortex-a9-scu", },
28 { .compatible = "arm,cortex-a5-scu", },
33 { .compatible = "arm,core-module-integrator", },
34 { .compatible = "arm,realview-eb-syscon", },
35 { .compatible = "arm,realview-pbx-syscon", },
66 /* The syscon contains the magic SMP start address registers */ in realview_smp_prepare_cpus()
[all …]
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
33 const: hisilicon,hi6220-sysctrl
[all …]

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