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/linux/tools/testing/selftests/rseq/
H A Dparam_test.c1 // SPDX-License-Identifier: LGPL-2.1
44 static __thread __attribute__((tls_model("initial-exec")))
49 static __thread __attribute__((tls_model("initial-exec"), unused))
113 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
204 "addiu " INJECT_ASM_REG ", -1\n\t" \
226 "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
250 "l.addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
269 if (loc_nr_loops == -1 && opt_modulo) { \
270 if (yield_mod_cnt == opt_modulo - 1) { \
329 int rseq_membarrier_expedited(int cpu) in rseq_membarrier_expedited() argument
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/linux/arch/loongarch/kvm/intc/
H A Deiointc.c1 // SPDX-License-Identifier: GPL-2.0
12 int ipnum, cpu, cpuid, irq; in eiointc_set_sw_coreisr() local
16 ipnum = (s->ipmap >> (irq / 32 * 8)) & 0xff; in eiointc_set_sw_coreisr()
17 if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) { in eiointc_set_sw_coreisr()
22 cpuid = ((u8 *)s->coremap)[irq]; in eiointc_set_sw_coreisr()
23 vcpu = kvm_get_vcpu_by_cpuid(s->kvm, cpuid); in eiointc_set_sw_coreisr()
27 cpu = vcpu->vcpu_id; in eiointc_set_sw_coreisr()
28 if (test_bit(irq, (unsigned long *)s->coreisr[cpu])) in eiointc_set_sw_coreisr()
29 __set_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
31 __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
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H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
15 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_set()
16 status = vcpu->arch.ipi_state.status; in ipi_set()
17 vcpu->arch.ipi_state.status |= data; in ipi_set()
18 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_set()
27 int cpu; in ipi_send() local
30 cpu = ((data & 0xffffffff) >> 16) & 0x3ff; in ipi_send()
31 vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu); in ipi_send()
33 kvm_err("%s: invalid target cpu: %d\n", __func__, cpu); in ipi_send()
45 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_clear()
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/linux/arch/arm/mach-zynq/
H A Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
18 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
33 * zynq_slcr_write - Write to a register in SLCR block
36 * @offset: Register offset in SLCR block
40 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
42 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
46 * zynq_slcr_read - Read a register in SLCR block
49 * @offset: Register offset in SLCR block
53 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
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/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_coherency.c2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
36 cpu = kmap_local_page(page) + offset_in_page(offset); in cpu_set()
39 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
41 *cpu = v; in cpu_set()
44 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
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/linux/arch/x86/include/asm/uv/
H A Duv_hub.h9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
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/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3.c1 // SPDX-License-Identifier: GPL-2.0
48 GUEST_ASSERT(count--); in gicv3_gicd_wait_for_rwp()
53 static inline volatile void *gicr_base_cpu(u32 cpu) in gicr_base_cpu() argument
56 return GICR_BASE_GVA + cpu * SZ_64K * 2; in gicr_base_cpu()
59 static void gicv3_gicr_wait_for_rwp(u32 cpu) in gicv3_gicr_wait_for_rwp() argument
63 while (readl(gicr_base_cpu(cpu) + GICR_CTLR) & GICR_CTLR_RWP) { in gicv3_gicr_wait_for_rwp()
64 GUEST_ASSERT(count--); in gicv3_gicr_wait_for_rwp()
124 * All other fields are read-only, so no need to read CTLR first. In in gicv3_set_eoi_split()
132 u32 gicv3_reg_readl(u32 cpu_or_dist, u64 offset) in gicv3_reg_readl() argument
136 return readl(base + offset); in gicv3_reg_readl()
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/linux/arch/x86/kernel/apic/
H A Dx2apic_savic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Secure AVIC Support (SEV-SNP Guests)
12 #include <linux/percpu-defs.h>
31 static inline void *get_reg_bitmap(unsigned int cpu, unsigned int offset) in get_reg_bitmap() argument
33 return &per_cpu_ptr(savic_page, cpu)->regs[offset]; in get_reg_bitmap()
36 static inline void update_vector(unsigned int cpu, unsigned int offset, in update_vector() argument
39 void *bitmap = get_reg_bitmap(cpu, offset); in update_vector()
51 * result in #VC exception (for non-accelerated register accesses)
95 "APIC register read offset 0x%x not aligned at 16 bytes", reg)) in savic_read()
98 /* IRR and ALLOWED_IRR offset range */ in savic_read()
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/linux/drivers/gpu/drm/lima/
H A Dlima_vm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
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/linux/arch/x86/platform/uv/
H A Duv_nmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpu.h>
37 * Handle system-wide NMI events generated by the global 'power nmi' command.
39 * Basic operation is to field the NMI interrupt on each CPU and wait
40 * until all CPU's have arrived into the nmi handler. If some CPU's do not
50 * second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
66 /* Non-zero indicates newer SMM NMI handler present */
83 #define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset)) argument
91 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
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/linux/arch/arm/mach-hisi/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
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/linux/tools/perf/arch/arm/util/
H A Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
71 static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, struct perf_cpu cpu);
72 static int cs_etm_get_ro(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path, __u64 *val);
73 static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path);
76 struct perf_cpu cpu) in cs_etm_get_version() argument
78 if (cs_etm_is_ete(cs_etm_pmu, cpu)) in cs_etm_get_version()
80 else if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0])) in cs_etm_get_version()
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/linux/arch/s390/mm/
H A Dmaccess.c1 // SPDX-License-Identifier: GPL-2.0
3 * Access kernel memory without faulting -- s390 specific implementation.
14 #include <linux/cpu.h>
17 #include <asm/asm-extable.h>
30 unsigned long aligned, offset, count; in s390_kernel_write_odd() local
34 offset = (unsigned long) dst & 7UL; in s390_kernel_write_odd()
35 size = min(8UL - offset, size); in s390_kernel_write_odd()
36 count = size - 1; in s390_kernel_write_odd()
46 : "a" (&tmp), "a" (&tmp[offset]), "a" (src) in s390_kernel_write_odd()
52 * __s390_kernel_write - write to kernel memory bypassing DAT
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/linux/include/linux/
H A Drelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi (zanussi@us.ibm.com), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour (karim@opersys.com)
48 * Per-cpu relay channel buffer
53 void *data; /* start of current sub-buffer */
54 size_t offset; /* current offset into sub-buffer */ member
55 size_t subbufs_produced; /* count of sub-buffers produced */
56 size_t subbufs_consumed; /* count of sub-buffers consumed */
66 size_t *padding; /* padding counts per sub-buffer */
69 unsigned int cpu; /* this buf's cpu */ member
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H A Dnd.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
41 * struct nvdimm_pmu - data structure for nvdimm perf driver
44 * @cpu: designated cpu for counter access.
45 * @node: node for cpu hotplug notifier link.
46 * @cpuhp_state: state for cpu hotplug notification.
47 * @arch_cpumask: cpumask to get designated cpu for counter access.
52 int cpu; member
72 return -ENXIO; in register_nvdimm_pmu()
90 * struct nd_namespace_common - core infrastructure of a namespace
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/linux/drivers/macintosh/
H A Dwindfarm_pm121.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * that none of the code has been re-used, it's a complete
17 * re-implementation
21 * controls with a tiny difference. The control-ids of hard-drive-fan
22 * and cpu-fan is swapped.
28 * new_min = ((((average_power * slope) >> 16) + offset) >> 16) + min_value
34 * offset : -19563152
38 * offset : -15650652
44 * offset : -15650652
48 * offset : -19563152
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/linux/tools/power/x86/turbostat/
H A Dturbostat.83 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv
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/linux/arch/x86/kernel/cpu/mce/
H A Damd.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
17 #include <linux/cpu.h>
49 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
151 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
158 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
159 if (!b->hwid) in smca_get_bank_type()
162 return b->hwid->bank_type; in smca_get_bank_type()
224 * So to define a unique name for each bank, we use a temp c-string to append
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/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.81 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "soc-slider: --soc-slider-balance # | --soc-slider-offset # | --platform-profile <name>"
20 .RB "value: # | default | performance | balance-performance | balance-power | power"
23 displays and updates energy-performance policy settings specific to
27 While \fBx86_energy_perf_policy\fP can manage energy-performance policy
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/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
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/linux/block/
H A Dblk-mq-cpumap.c1 // SPDX-License-Identifier: GPL-2.0
3 * CPU <-> hardware queue mapping helpers
5 * Copyright (C) 2013-2014 Jens Axboe
12 #include <linux/cpu.h>
18 #include "blk-mq.h"
30 * blk_mq_num_possible_queues - Calc nr of queues for multiqueue devices
45 * blk_mq_num_online_queues - Calc nr of queues for multiqueue devices
62 unsigned int queue, cpu, nr_masks; in blk_mq_map_queues() local
64 masks = group_cpus_evenly(qmap->nr_queues, &nr_masks); in blk_mq_map_queues()
66 for_each_possible_cpu(cpu) in blk_mq_map_queues()
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/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
56 unsigned long value, offset; in clear_nps_pkt_err_intr() local
64 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
65 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
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/linux/drivers/soc/samsung/
H A Dexynos-pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
6 // Exynos - CPU PMU(Power Management Unit) support
22 #include <linux/soc/samsung/exynos-regs-pmu.h>
23 #include <linux/soc/samsung/exynos-pmu.h>
25 #include "exynos-pmu.h"
33 * Serialization lock for CPU hot plug and cpuidle ACPM hint
48 void pmu_raw_writel(u32 val, u32 offset) in pmu_raw_writel() argument
50 writel_relaxed(val, pmu_base_addr + offset); in pmu_raw_writel()
53 u32 pmu_raw_readl(u32 offset) in pmu_raw_readl() argument
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/linux/scripts/gdb/linux/
H A Dcpus.py4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
31 raise gdb.GdbError("Sorry, obtaining the current CPU is not yet "
35 def per_cpu(var_ptr, cpu): argument
36 if cpu == -1:
37 cpu = get_current_cpu()
39 offset = gdb.parse_and_eval(
40 "trap_block[{0}].__per_cpu_base".format(str(cpu)))
43 offset = gdb.parse_and_eval(
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/linux/kernel/trace/
H A Dfgraph.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2008-2009 Frederic Weisbecker <fweisbec@gmail.com>
34 * bits: 0 - 9 offset in words from the previous ftrace_ret_stack
36 * bits: 10 - 11 Type of storage
37 * 0 - reserved
38 * 1 - bitmap of fgraph_array index
39 * 2 - reserved data
42 * bits: 12 - 27 The bitmap of fgraph_ops fgraph_array index
43 * That is, it's a bitmask of 0-15 (16 bits)
53 * bits: 12 - 17 The size in words that is stored
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