Home
last modified time | relevance | path

Searched +full:cpu +full:- +full:offset (Results 1 – 25 of 1017) sorted by relevance

12345678910>>...41

/linux/drivers/thermal/intel/
H A Dintel_tcc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_tcc.c - Library for Intel TCC (thermal control circuitry) MSR access
10 #include <asm/intel-family.h>
14 * struct temp_masks - Bitmasks for temperature readings
15 * @tcc_offset: TCC offset in MSR_TEMPERATURE_TARGET
129 memcpy(&intel_tcc_temp_masks, (const void *)id->driver_data, in intel_tcc_init()
141 * intel_tcc_get_offset_mask() - Returns the bitmask to read TCC offset
143 * Get the model-specific bitmask to extract TCC_OFFSET from the MSR
145 * not support TCC offset.
147 * Return: The model-specific bitmask for TCC offset.
[all …]
/linux/tools/testing/selftests/rseq/
H A Dparam_test.c1 // SPDX-License-Identifier: LGPL-2.1
44 static __thread __attribute__((tls_model("initial-exec")))
49 static __thread __attribute__((tls_model("initial-exec"), unused))
113 "ahi %%" INJECT_ASM_REG ", -1\n\t" \
204 "addiu " INJECT_ASM_REG ", -1\n\t" \
226 "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
250 "l.addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \
269 if (loc_nr_loops == -
302 rseq_membarrier_expedited(int cpu) rseq_membarrier_expedited() argument
327 rseq_membarrier_expedited(int cpu) rseq_membarrier_expedited() argument
388 intptr_t offset; global() member
405 intptr_t offset; global() member
417 int cpu; rseq_this_cpu_lock() local
443 rseq_percpu_unlock(struct percpu_lock * lock,int cpu) rseq_percpu_unlock() argument
464 int cpu = rseq_this_cpu_lock(&data->lock); test_percpu_spinlock_thread() local
544 int cpu; test_percpu_inc_thread() local
611 int cpu; this_cpu_list_push() local
642 int cpu; this_cpu_list_pop() local
647 long offset; this_cpu_list_pop() local
675 __percpu_list_pop(struct percpu_list * list,int cpu) __percpu_list_pop() argument
787 int cpu; this_cpu_buffer_push() local
792 intptr_t offset; this_cpu_buffer_push() local
821 int cpu; this_cpu_buffer_pop() local
825 intptr_t offset; this_cpu_buffer_pop() local
856 __percpu_buffer_pop(struct percpu_buffer * buffer,int cpu) __percpu_buffer_pop() argument
859 intptr_t offset; __percpu_buffer_pop() local
988 int cpu; this_cpu_memcpy_buffer_push() local
991 intptr_t *targetptr_final, newval_final, offset; this_cpu_memcpy_buffer_push() local
1028 int cpu; this_cpu_memcpy_buffer_pop() local
1031 intptr_t *targetptr_final, newval_final, offset; this_cpu_memcpy_buffer_pop() local
1067 __percpu_memcpy_buffer_pop(struct percpu_memcpy_buffer * buffer,struct percpu_memcpy_buffer_node * item,int cpu) __percpu_memcpy_buffer_pop() argument
1069 intptr_t offset; __percpu_memcpy_buffer_pop() local
1250 int cpu = get_current_cpu_id(); test_membarrier_worker_thread() local
[all...]
/linux/Documentation/core-api/
H A Dthis_cpu_ops.rst8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
65 ------------------------------------
[all …]
/linux/arch/arm/mach-zynq/
H A Dslcr.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
18 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
33 * zynq_slcr_write - Write to a register in SLCR block
36 * @offset: Register offset in SLCR block
40 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
42 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
46 * zynq_slcr_read - Read a register in SLCR block
49 * @offset: Register offset in SLCR block
53 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
[all …]
/linux/arch/loongarch/kvm/intc/
H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
12 int cpu, action; in ipi_send() local
17 cpu = ((data & 0xffffffff) >> 16) & 0x3ff; in ipi_send()
18 vcpu = kvm_get_vcpu_by_cpuid(kvm, cpu); in ipi_send()
20 kvm_err("%s: invalid target cpu: %d\n", __func__, cpu); in ipi_send()
25 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_send()
26 status = vcpu->arch.ipi_state.status; in ipi_send()
27 vcpu->arch.ipi_state.status |= action; in ipi_send()
28 spin_unlock(&vcpu->arch.ipi_state.lock); in ipi_send()
40 spin_lock(&vcpu->arch.ipi_state.lock); in ipi_clear()
[all …]
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_coherency.c2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
36 cpu = kmap_local_page(page) + offset_in_page(offset); in cpu_set()
39 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
41 *cpu = v; in cpu_set()
44 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
[all …]
/linux/tools/testing/selftests/kvm/lib/aarch64/
H A Dgic_v3.c
/linux/arch/x86/include/asm/uv/
H A Duv_hub.h9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
[all …]
/linux/kernel/time/
H A Dtimer_list.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
49 SEQ_printf(m, " #%d: <%pK>, %ps", idx, taddr, timer->function); in print_timer()
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
[all …]
/linux/drivers/clk/qcom/
H A Dkrait-cc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
16 #include "clk-krait.h"
52 mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw); in krait_notifier_cb()
53 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
54 mux->reparent = false; in krait_notifier_cb()
61 if (!mux->reparent) in krait_notifier_cb()
62 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
63 mux->old_index); in krait_notifier_cb()
74 mux->clk_nb.notifier_call = krait_notifier_cb; in krait_notifier_register()
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_vm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
/linux/arch/x86/platform/uv/
H A Duv_nmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpu.h>
37 * Handle system-wide NMI events generated by the global 'power nmi' command.
39 * Basic operation is to field the NMI interrupt on each CPU and wait
40 * until all CPU's have arrived into the nmi handler. If some CPU's do not
50 * second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
66 /* Non-zero indicates newer SMM NMI handler present */
83 #define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset)) argument
91 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
[all …]
/linux/arch/arm/mach-hisi/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
[all …]
/linux/tools/perf/arch/arm/util/
H A Dcs-etm.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
71 static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, struct perf_cpu cpu);
72 static int cs_etm_get_ro(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path, __u64 *val);
73 static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path);
76 struct perf_cpu cpu) in cs_etm_get_version() argument
78 if (cs_etm_is_ete(cs_etm_pmu, cpu)) in cs_etm_get_version()
80 else if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0])) in cs_etm_get_version()
[all …]
/linux/drivers/media/pci/tw68/
H A Dtw68-risc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * acknowledged. Full credit goes to them - any problems within this code
25 * @sglist: pointer to "scatter-gather list" of buffer pointers
26 * @offset: offset to target memory buffer
27 * @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync
34 unsigned int offset, u32 sync_line, in tw68_risc_field() argument
57 while (offset && offset >= sg_dma_len(sg)) { in tw68_risc_field()
58 offset -= sg_dma_len(sg); in tw68_risc_field()
61 if (bpl <= sg_dma_len(sg) - offset) { in tw68_risc_field()
64 /* (offset<<12) |*/ bpl); in tw68_risc_field()
[all …]
/linux/include/linux/
H A Drelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi (zanussi@us.ibm.com), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour (karim@opersys.com)
32 * Per-cpu relay channel buffer
37 void *data; /* start of current sub-buffer */
38 size_t offset; /* current offset into sub-buffer */ member
39 size_t subbufs_produced; /* count of sub-buffers produced */
40 size_t subbufs_consumed; /* count of sub-buffers consumed */
49 size_t *padding; /* padding counts per sub-buffer */
53 unsigned int cpu; /* this buf's cpu */ member
[all …]
H A Dnd.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
41 * struct nvdimm_pmu - data structure for nvdimm perf driver
44 * @cpu: designated cpu for counter access.
45 * @node: node for cpu hotplug notifier link.
46 * @cpuhp_state: state for cpu hotplug notification.
47 * @arch_cpumask: cpumask to get designated cpu for counter access.
52 int cpu; member
72 return -ENXIO; in register_nvdimm_pmu()
90 * struct nd_namespace_common - core infrastructure of a namespace
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
[all …]
/linux/drivers/macintosh/
H A Dwindfarm_pm121.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * that none of the code has been re-used, it's a complete
17 * re-implementation
21 * controls with a tiny difference. The control-ids of hard-drive-fan
22 * and cpu-fan is swapped.
28 * new_min = ((((average_power * slope) >> 16) + offset) >> 16) + min_value
34 * offset : -19563152
38 * offset : -15650652
44 * offset : -15650652
48 * offset : -19563152
[all …]
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
56 unsigned long value, offset; in clear_nps_pkt_err_intr() local
64 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
65 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dqcom-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
14 pattern: "^(watchdog|timer)@[0-9a-f]+$"
18 - items:
19 - enum:
20 - qcom,kpss-wdt-ipq4019
[all …]
/linux/include/trace/events/
H A Drcu.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 * "Start <activity>" -- Mark the start of the specified activity,
22 * "End <activity>" -- Mark the end of the specified activity.
38 __entry->s = s;
41 TP_printk("%s", __entry->s)
47 * Tracepoint for grace-period events. Takes a string identifying the
48 * RCU flavor, the grace-period number, and a string identifying the
49 * grace-period-related event as follows:
51 * "AccReadyCB": CPU accelerates new callbacks to RCU_NEXT_READY_TAIL.
52 * "AccWaitCB": CPU accelerates new callbacks to RCU_WAIT_TAIL.
[all …]
/linux/include/uapi/drm/
H A Dv3d_drm.h2 * Copyright © 2014-2018 Broadcom
71 /* struct drm_v3d_extension - ioctl extensions
73 * Linked-list of generic extensions where the id identify which struct is
90 /* struct drm_v3d_sem - wait/signal semaphore
114 * struct drm_v3d_multi_sync - ioctl extension to add support multiples
139 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
163 * clients -- that is left up to the submitter to control
171 /* Offset of the render command list.
175 * of tiles (in the case of RCL-only blits).
179 * submitted by other clients -- that is left up to the
[all …]
/linux/kernel/trace/
H A Dfgraph.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2008-2009 Frederic Weisbecker <fweisbec@gmail.com>
34 * bits: 0 - 9 offset in words from the previous ftrace_ret_stack
36 * bits: 10 - 11 Type of storage
37 * 0 - reserved
38 * 1 - bitmap of fgraph_array index
39 * 2 - reserved data
42 * bits: 12 - 27 The bitmap of fgraph_ops fgraph_array index
43 * That is, it's a bitmask of 0-15 (16 bits)
53 * bits: 12 - 17 The size in words that is stored
[all …]
/linux/kernel/irq/
H A Dipi.c1 // SPDX-License-Identifier: GPL-2.0
15 * irq_reserve_ipi() - Setup an IPI to destination cpumask
19 * Allocate a virq that can be used to send IPI to any CPU in dest mask.
26 unsigned int nr_irqs, offset; in irq_reserve_ipi() local
32 return -EINVAL; in irq_reserve_ipi()
37 return -EINVAL; in irq_reserve_ipi()
43 return -EINVAL; in irq_reserve_ipi()
54 offset = 0; in irq_reserve_ipi()
59 * The IPI requires a separate HW irq on each CPU. We require in irq_reserve_ipi()
64 offset = cpumask_first(dest); in irq_reserve_ipi()
[all …]

12345678910>>...41