| /linux/arch/loongarch/kvm/intc/ |
| H A D | eiointc.c | 1 // SPDX-License-Identifier: GPL-2.0
12 int ipnum, cpu, cpuid, irq; in eiointc_set_sw_coreisr() local
16 ipnum = s->ipmap.reg_u8[irq / 32]; in eiointc_set_sw_coreisr()
17 if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) { in eiointc_set_sw_coreisr()
22 cpuid = s->coremap.reg_u8[irq]; in eiointc_set_sw_coreisr()
23 vcpu = kvm_get_vcpu_by_cpuid(s->kvm, cpuid); in eiointc_set_sw_coreisr()
27 cpu = vcpu->vcpu_id; in eiointc_set_sw_coreisr()
28 if (test_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu])) in eiointc_set_sw_coreisr()
29 __set_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
31 __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); in eiointc_set_sw_coreisr()
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| /linux/arch/arm/mach-zynq/ |
| H A D | slcr.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
18 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
33 * zynq_slcr_write - Write to a register in SLCR block
36 * @offset: Register offset in SLCR block
40 static int zynq_slcr_write(u32 val, u32 offset) in zynq_slcr_write() argument
42 return regmap_write(zynq_slcr_regmap, offset, val); in zynq_slcr_write()
46 * zynq_slcr_read - Read a register in SLCR block
49 * @offset: Register offset in SLCR block
53 static int zynq_slcr_read(u32 *val, u32 offset) in zynq_slcr_read() argument
[all …]
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| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_coherency.c | 2 * SPDX-License-Identifier: MIT
23 static int cpu_set(struct context *ctx, unsigned long offset, u32 v) in cpu_set() argument
27 u32 *cpu; in cpu_set() local
30 i915_gem_object_lock(ctx->obj, NULL); in cpu_set()
31 err = i915_gem_object_prepare_write(ctx->obj, &needs_clflush); in cpu_set()
35 page = i915_gem_object_get_page(ctx->obj, offset >> PAGE_SHIFT); in cpu_set()
36 cpu = kmap_local_page(page) + offset_in_page(offset); in cpu_set()
39 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
41 *cpu = v; in cpu_set()
44 drm_clflush_virt_range(cpu, sizeof(*cpu)); in cpu_set()
[all …]
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| /linux/arch/x86/include/asm/uv/ |
| H A D | uv_hub.h | 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
33 * M - The low M bits of a physical address represent the offset
38 * N - Number of bits in the node portion of a socket physical
41 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
44 * right shift the NASID by 1 to exclude the always-zero bit.
47 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
50 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
53 * GPA - (global physical address) a socket physical address converted
62 * +--------------------------------+---------------------+
64 * +--------------------------------+---------------------+
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| /linux/kernel/time/ |
| H A D | timer_list.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "tick-internal.h"
21 int cpu; member
28 * to the console (on SysRq-Q):
50 SEQ_printf(m, ", S:%02x", timer->state); in print_timer()
52 SEQ_printf(m, " # expires at %Lu-%Lu nsecs [in %Ld to %Ld nsecs]\n", in print_timer()
55 (long long)(ktime_to_ns(hrtimer_get_softexpires(timer)) - now), in print_timer()
56 (long long)(ktime_to_ns(hrtimer_get_expires(timer)) - now)); in print_timer()
73 raw_spin_lock_irqsave(&base->cpu_base->lock, flags); in print_active_timers()
75 curr = timerqueue_getnext(&base->active); in print_active_timers()
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| /linux/tools/perf/pmu-events/ |
| H A D | empty-pmu-events.c | 2 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <pmu-events/pmu-events.h>
12 int offset; member
22 /* offset=0 */ "software\000"
23 /* offset=9 */ "cpu-clock\000software\000Per-CPU high-resolution timer based event\000config=0\000\…
24 /* offset=87 */ "task-clock\000software\000Per-task high-resolution timer based event\000config=1\0…
25 /* offset=167 */ "faults\000software\000Number of page faults [This event is an alias of page-fault…
26 /* offset=262 */ "page-faults\000software\000Number of page faults [This event is an alias of fault…
27 /* offset=357 */ "context-switches\000software\000Number of context switches [This event is an alia…
28 /* offset=458 */ "cs\000software\000Number of context switches [This event is an alias of context-s…
[all …]
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| /linux/arch/x86/kernel/apic/ |
| H A D | x2apic_savic.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Secure AVIC Support (SEV-SNP Guests)
12 #include <linux/percpu-defs.h>
31 static inline void *get_reg_bitmap(unsigned int cpu, unsigned int offset) in get_reg_bitmap() argument
33 return &per_cpu_ptr(savic_page, cpu)->regs[offset]; in get_reg_bitmap()
36 static inline void update_vector(unsigned int cpu, unsigned int offset, in update_vector() argument
39 void *bitmap = get_reg_bitmap(cpu, offset); in update_vector()
51 * result in #VC exception (for non-accelerated register accesses)
95 "APIC register read offset 0x%x not aligned at 16 bytes", reg)) in savic_read()
98 /* IRR and ALLOWED_IRR offset range */ in savic_read()
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| /linux/drivers/gpu/drm/lima/ |
| H A D | lima_vm.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
5 #include <linux/dma-mapping.h>
26 #define LIMA_VM_PT_MASK ((1 << LIMA_VM_PD_SHIFT) - 1)
27 #define LIMA_VM_BT_MASK ((1 << LIMA_VM_PB_SHIFT) - 1)
43 vm->bts[pbe].cpu[bte] = 0; in lima_vm_unmap_range()
52 if (!vm->bts[pbe].cpu) { in lima_vm_map_page()
57 vm->bts[pbe].cpu = dma_alloc_wc( in lima_vm_map_page()
58 vm->dev->dev, LIMA_PAGE_SIZE << LIMA_VM_NUM_PT_PER_BT_SHIFT, in lima_vm_map_page()
59 &vm->bts[pbe].dma, GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); in lima_vm_map_page()
[all …]
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| /linux/arch/arm/mach-hisi/ |
| H A D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
23 void hi3xxx_set_cpu_jump(int cpu, void *jump_addr) in hi3xxx_set_cpu_jump() argument
25 cpu = cpu_logical_map(cpu); in hi3xxx_set_cpu_jump()
26 if (!cpu || !ctrl_base) in hi3xxx_set_cpu_jump()
28 writel_relaxed(__pa_symbol(jump_addr), ctrl_base + ((cpu - 1) << 2)); in hi3xxx_set_cpu_jump()
31 int hi3xxx_get_cpu_jump(int cpu) in hi3xxx_get_cpu_jump() argument
33 cpu = cpu_logical_map(cpu); in hi3xxx_get_cpu_jump()
34 if (!cpu || !ctrl_base) in hi3xxx_get_cpu_jump()
36 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
[all …]
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| /linux/arch/x86/platform/uv/ |
| H A D | uv_nmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2007-2017 Silicon Graphics, Inc. All rights reserved.
10 #include <linux/cpu.h>
37 * Handle system-wide NMI events generated by the global 'power nmi' command.
39 * Basic operation is to field the NMI interrupt on each CPU and wait
40 * until all CPU's have arrived into the nmi handler. If some CPU's do not
50 * second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
66 /* Non-zero indicates newer SMM NMI handler present */
83 #define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset)) argument
91 static atomic_t uv_nmi_cpu = ATOMIC_INIT(-1);
[all …]
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| /linux/tools/perf/arch/arm/util/ |
| H A D | cs-etm.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/coresight-pmu.h>
18 #include "cs-etm.h"
29 #include "../../../util/cs-etm.h"
71 static bool cs_etm_is_ete(struct perf_pmu *cs_etm_pmu, struct perf_cpu cpu);
72 static int cs_etm_get_ro(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path, __u64 *val);
73 static bool cs_etm_pmu_path_exists(struct perf_pmu *pmu, struct perf_cpu cpu, const char *path);
76 struct perf_cpu cpu) in cs_etm_get_version() argument
78 if (cs_etm_is_ete(cs_etm_pmu, cpu)) in cs_etm_get_version()
80 else if (cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0])) in cs_etm_get_version()
[all …]
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| /linux/arch/s390/mm/ |
| H A D | maccess.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Access kernel memory without faulting -- s390 specific implementation.
14 #include <linux/cpu.h>
17 #include <asm/asm-extable.h>
30 unsigned long aligned, offset, count; in s390_kernel_write_odd() local
34 offset = (unsigned long) dst & 7UL; in s390_kernel_write_odd()
35 size = min(8UL - offset, size); in s390_kernel_write_odd()
36 count = size - 1; in s390_kernel_write_odd()
46 : "a" (&tmp), "a" (&tmp[offset]), "a" (src) in s390_kernel_write_odd()
52 * __s390_kernel_write - write to kernel memory bypassing DAT
[all …]
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| /linux/include/linux/ |
| H A D | relay.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2002, 2003 - Tom Zanussi (zanussi@us.ibm.com), IBM Corp
6 * Copyright (C) 1999, 2000, 2001, 2002 - Karim Yaghmour (karim@opersys.com)
48 * Per-cpu relay channel buffer
53 void *data; /* start of current sub-buffer */
54 size_t offset; /* current offset into sub-buffer */ member
55 size_t subbufs_produced; /* count of sub-buffers produced */
56 size_t subbufs_consumed; /* count of sub-buffers consumed */
66 size_t *padding; /* padding counts per sub-buffer */
69 unsigned int cpu; /* this buf's cpu */ member
[all …]
|
| H A D | nd.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
41 * struct nvdimm_pmu - data structure for nvdimm perf driver
44 * @cpu: designated cpu for counter access.
45 * @node: node for cpu hotplug notifier link.
46 * @cpuhp_state: state for cpu hotplug notification.
47 * @arch_cpumask: cpumask to get designated cpu for counter access.
52 int cpu; member
72 return -ENXIO; in register_nvdimm_pmu()
90 * struct nd_namespace_common - core infrastructure of a namespace
[all …]
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| /linux/drivers/virt/coco/arm-cca-guest/ |
| H A D | arm-cca-guest.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/arm-smccc.h>
18 * struct arm_cca_token_info - a descriptor for the token buffer.
22 * @offset: Offset within granule to start of buffer in bytes
29 unsigned long offset; member
39 info->result = rsi_attestation_token_init(info->challenge, in arm_cca_attestation_init()
40 info->challenge_size); in arm_cca_attestation_init()
44 * arm_cca_attestation_continue - Retrieve the attestation token data.
50 * token retrieval operation must be requested on the same CPU on which the
52 * This helper function is therefore scheduled on the same CPU multiple
[all …]
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| /linux/tools/power/x86/turbostat/ |
| H A D | turbostat.8 | 3 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
32 msrDDD is a decimal offset, eg. msr16
33 msr0xXXX is a hex offset, eg. msr0x10
[all …]
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| /linux/arch/mips/boot/dts/mti/ |
| H A D | sead3.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
26 cpu@0 {
36 cpu_intc: interrupt-controller {
[all …]
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| /linux/block/ |
| H A D | blk-mq-cpumap.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * CPU <-> hardware queue mapping helpers
5 * Copyright (C) 2013-2014 Jens Axboe
12 #include <linux/cpu.h>
18 #include "blk-mq.h"
30 * blk_mq_num_possible_queues - Calc nr of queues for multiqueue devices
45 * blk_mq_num_online_queues - Calc nr of queues for multiqueue devices
62 unsigned int queue, cpu, nr_masks; in blk_mq_map_queues() local
64 masks = group_cpus_evenly(qmap->nr_queues, &nr_masks); in blk_mq_map_queues()
66 for_each_possible_cpu(cpu) in blk_mq_map_queues()
[all …]
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| /linux/drivers/crypto/cavium/nitrox/ |
| H A D | nitrox_isr.c | 1 // SPDX-License-Identifier: GPL-2.0
15 * - NPS packet ring, AQMQ ring and ZQMQ ring
24 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
37 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
56 unsigned long value, offset; in clear_nps_pkt_err_intr() local
64 offset = NPS_PKT_SLC_ERR_TYPE; in clear_nps_pkt_err_intr()
65 value = nitrox_read_csr(ndev, offset); in clear_nps_pkt_err_intr()
66 nitrox_write_csr(ndev, offset, value); in clear_nps_pkt_err_intr()
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| /linux/drivers/macintosh/ |
| H A D | windfarm_pm121.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 * that none of the code has been re-used, it's a complete
17 * re-implementation
21 * controls with a tiny difference. The control-ids of hard-drive-fan
22 * and cpu-fan is swapped.
28 * new_min = ((((average_power * slope) >> 16) + offset) >> 16) + min_value
34 * offset : -19563152
38 * offset : -15650652
44 * offset : -15650652
48 * offset : -19563152
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| /linux/arch/x86/kernel/cpu/mce/ |
| H A D | amd.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
5 * Written by Jacob Shin - AMD, Inc.
17 #include <linux/cpu.h>
52 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
131 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
138 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
139 if (!b->hwid) in smca_get_bank_type()
142 return b->hwid->bank_type; in smca_get_bank_type()
212 * So to define a unique name for each bank, we use a temp c-string to append
[all …]
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| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | qcom-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
14 pattern: "^(watchdog|timer)@[0-9a-f]+$"
18 - items:
19 - enum:
20 - qcom,kpss-wdt-ipq4019
[all …]
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| /linux/scripts/gdb/linux/ |
| H A D | cpus.py | 4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
31 raise gdb.GdbError("Sorry, obtaining the current CPU is not yet "
35 def per_cpu(var_ptr, cpu): argument
36 if cpu == -1:
37 cpu = get_current_cpu()
39 offset = gdb.parse_and_eval(
40 "trap_block[{0}].__per_cpu_base".format(str(cpu)))
43 offset = gdb.parse_and_eval(
[all …]
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| /linux/include/uapi/drm/ |
| H A D | v3d_drm.h | 2 * Copyright © 2014-2018 Broadcom
71 /* struct drm_v3d_extension - ioctl extensions
73 * Linked-list of generic extensions where the id identify which struct is
90 /* struct drm_v3d_sem - wait/signal semaphore
114 * struct drm_v3d_multi_sync - ioctl extension to add support multiples
139 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
163 * clients -- that is left up to the submitter to control
171 /* Offset of the render command list.
175 * of tiles (in the case of RCL-onl
259 __u32 offset; global() member
278 __u64 offset; global() member
312 __u32 offset; global() member
404 __u32 offset; global() member
459 __u32 offset; global() member
490 __u32 offset; global() member
556 __u32 offset; global() member
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| /linux/kernel/trace/ |
| H A D | fgraph.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2008-2009 Frederic Weisbecker <fweisbec@gmail.com>
34 * bits: 0 - 9 offset in words from the previous ftrace_ret_stack
36 * bits: 10 - 11 Type of storage
37 * 0 - reserved
38 * 1 - bitmap of fgraph_array index
39 * 2 - reserved data
42 * bits: 12 - 27 The bitmap of fgraph_ops fgraph_array index
43 * That is, it's a bitmask of 0-15 (16 bits)
53 * bits: 12 - 17 The size in words that is stored
[all …]
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