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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json4 "Counter": "0,1,2,3",
11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
12 "Counter": "0,1,2,3",
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
24 "Counter": "0,1,2,3",
36 "Counter": "0,1,2,3",
48 "Counter": "0,1,2,3",
60 "Counter": "0,1,2,3",
72 "Counter": "0,1,2,3",
84 "Counter": "0,1,2,3",
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/freebsd/sys/contrib/device-tree/Bindings/
H A Dnuma.txt6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
33 gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
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H A Dexynos5422-odroidhc1.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include "exynos5422-odroid-core.dtsi"
16 compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \
19 led-controller {
20 compatible = "pwm-leds";
22 led-1 {
26 pwm-names = "pwm2";
27 max-brightness = <255>;
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H A Dexynos5420-arndale-octa.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos5420-cpus.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/clock/samsung,s2mps11.h>
19 compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
32 stdout-path = "serial3:115200n8";
36 compatible = "samsung,secure-firmware";
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/freebsd/lib/libkvm/
H A Dkvm_getpcpu.313 .\" 3. Neither the name of the author nor the names of any co-contributors
36 .Nd access per-CPU data
45 .Fn kvm_dpcpu_setcpu "kvm_t *kd" "u_int cpu"
51 .Fn kvm_getpcpu "kvm_t *kd" "int cpu"
53 .Fn kvm_read_zpcpu "kvm_t *kd" "u_long base" "void *buf" "size_t size" "int cpu"
62 functions are used to access the per-CPU data of active processors in the
65 Per-CPU storage comes in two flavours: data stored directly in a
67 associated with each CPU, and dynamic per-CPU storage (DPCPU), in which a
68 single kernel symbol refers to different data depending on what CPU it is
81 function returns a buffer holding the per-CPU data for a single CPU.
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/freebsd/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Duncore-other.json4 "Counter": "0,1,2,3",
14 "Counter": "0,1,2,3",
24 "Counter": "0,1,2,3",
34 "Counter": "0,1,2,3",
44 "Counter": "0,1,2,3",
54 "Counter": "0,1,2,3",
64 "Counter": "0,1,2,3",
72 "Counter": "0,1,2,3",
81 "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH",
82 "Counter": "0,1,2,3",
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/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
23 cpu = <&CPU0>;
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H A Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
20 cpu = <&CPU0>;
23 cpu = <&CPU1>;
26 cpu = <&CPU2>;
29 cpu = <&CPU3>;
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/freebsd/lib/libpmc/
H A Dpmc_capabilities.31 .\" Copyright (c) 2007-2008 Joseph Koshy. All rights reserved.
46 .Fn pmc_npmc "int cpu"
48 .Fn pmc_pmcinfo "int cpu" "struct pmc_pmcinfo **pmc_info"
68 .Xr pmc 3 .
79 .Bl -tag -width "pm_classes" -offset indent -compact
81 Specifies the CPU type.
85 Specifies the number of PMC rows per CPU.
97 is a convenience function that returns the maximum CPU number in
106 in the CPU specified by argument
107 .Fa cpu .
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/freebsd/sys/dev/asmc/
H A Dasmcvar.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
58 #define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
60 bus_write_1(sc->sc_ioport, 0x00, val)
66 #define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
68 bus_write_1(sc->sc_ioport, 0x04, val)
75 #define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
136 * fourth the Mac Pro 8-core and finally the MacBook Air.
173 #define ASMC_MB71_TEMPDESCS { "Enclosure Bottom 0", "Battery 1", "Battery 2", "CPU Package", "CPU P…
197 "graphics", "cpu", "cpu2", "unknown1", \
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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H A Dcpu-capacity.txt2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
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/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-qcom-hw.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
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/freebsd/sys/contrib/device-tree/Bindings/opp/
H A Dopp-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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H A Dopp-v2-kryo-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
36 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/
H A Dx86.c1 //===-- cpu_model/x86.c - Support for __cpu_model builtin --------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
19 #error This file is intended only for x86-based targets
145 // has some not one-to-one mapped in llvm.
156 // a cpu string with no X86_FEATURE_COMPAT features, which is required in
264 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
295 *rEDX = registers[3]; in getX86CpuIDAndInfo()
302 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
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/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt6592.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&sysirq>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@0 {
22 device_type = "cpu";
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/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@0 {
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/freebsd/sys/contrib/device-tree/src/c6x/
H A Dtms320c6678.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu@0 {
12 device_type = "cpu";
16 cpu@1 {
17 device_type = "cpu";
21 cpu@2 {
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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,saw2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 power-controller that transitions a piece of hardware (like a processor or
27 - enum:
28 - qcom,ipq4019-saw2-cpu
29 - qcom,ipq4019-saw2-l2
30 - qcom,ipq8064-saw2-cpu
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