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/linux/tools/testing/selftests/cpu-hotplug/
H A Dcpu-on-off-test.sh2 # SPDX-License-Identifier: GPL-2.0
5 # Kselftest framework requirement - SKIP code is 4.
18 taskset -p 01 $$
20 SYSFS=`mount -t sysfs | head -1 | awk '{ print $3 }'`
22 if [ ! -d "$SYSFS" ]; then
27 if ! ls $SYSFS/devices/system/cpu/cpu* > /dev/null 2>&1; then
28 echo $msg cpu hotplug is not supported >&2
32 echo "CPU online/offline summary:"
33 online_cpus=`cat $SYSFS/devices/system/cpu/online`
34 online_max=${online_cpus##*-}
[all …]
/linux/tools/perf/tests/
H A Dtopology.c1 // SPDX-License-Identifier: GPL-2.0
14 #define TEMPL "/tmp/perf-test-XXXXXX"
26 return -1; in get_temp()
44 session->evlist = evlist__new_default(); in session_write_header()
45 TEST_ASSERT_VAL("can't get evlist", session->evlist); in session_write_header()
46 session->evlist->session = session; in session_write_header()
48 perf_header__set_feat(&session->header, HEADER_CPU_TOPOLOGY); in session_write_header()
49 perf_header__set_feat(&session->header, HEADER_NRCPUS); in session_write_header()
50 perf_header__set_feat(&session->header, HEADER_ARCH); in session_write_header()
52 session->header.data_size += DATA_SIZE; in session_write_header()
[all …]
/linux/tools/perf/util/
H A Dcpumap.c1 // SPDX-License-Identifier: GPL-2.0
22 * CPU number.
30 __u32 bit_mask32 = 1U << (i & 31); in perf_record_cpu_map_data__test_bit()
32 __u64 bit_mask64 = ((__u64)1) << (i & 63); in perf_record_cpu_map_data__test_bit()
34 return (data->mask32_data.long_size == 4) in perf_record_cpu_map_data__test_bit()
35 ? (bit_word32 < data->mask32_data.nr) && in perf_record_cpu_map_data__test_bit()
36 (data->mask32_data.mask[bit_word32] & bit_mask32) != 0 in perf_record_cpu_map_data__test_bit()
37 : (bit_word64 < data->mask64_dat in perf_record_cpu_map_data__test_bit()
106 int cpu; cpu_map__from_mask() local
129 for (int cpu = data->range_cpu_data.start_cpu; cpu <= data->range_cpu_data.end_cpu; cpu_map__from_range() local
188 cpu__get_topology_int(int cpu,const char * name,int * value) cpu__get_topology_int() argument
198 cpu__get_socket_id(struct perf_cpu cpu) cpu__get_socket_id() argument
204 aggr_cpu_id__socket(struct perf_cpu cpu,void * data __maybe_unused) aggr_cpu_id__socket() argument
240 struct perf_cpu cpu; cpu_aggr_map__new() local
282 cpu__get_die_id(struct perf_cpu cpu) cpu__get_die_id() argument
289 aggr_cpu_id__die(struct perf_cpu cpu,void * data) aggr_cpu_id__die() argument
312 cpu__get_cluster_id(struct perf_cpu cpu) cpu__get_cluster_id() argument
319 aggr_cpu_id__cluster(struct perf_cpu cpu,void * data) aggr_cpu_id__cluster() argument
336 cpu__get_core_id(struct perf_cpu cpu) cpu__get_core_id() argument
342 aggr_cpu_id__core(struct perf_cpu cpu,void * data) aggr_cpu_id__core() argument
361 aggr_cpu_id__cpu(struct perf_cpu cpu,void * data) aggr_cpu_id__cpu() argument
375 aggr_cpu_id__node(struct perf_cpu cpu,void * data __maybe_unused) aggr_cpu_id__node() argument
383 aggr_cpu_id__global(struct perf_cpu cpu,void * data __maybe_unused) aggr_cpu_id__global() argument
518 cpu__get_node(struct perf_cpu cpu) cpu__get_node() argument
551 unsigned int cpu, mem; cpu__setup_cpunode_map() local
609 struct perf_cpu cpu = { .cpu = INT_MAX }; cpu_map__snprint() local
673 for (int cpu = last_cpu.cpu / 4 * 4; cpu >= 0; cpu -= 4) { cpu_map__snprint_mask() local
[all...]
/linux/arch/arm/mach-bcm/
H A Dplatsmp-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom STB CPU SMP and hotplug support for ARM
5 * Copyright (C) 2013-2014 Broadcom Corporation
22 #include <asm/mach-types.h>
27 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
40 CPU0_PWR_ZONE_CTRL_REG = 1,
52 * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
59 static int per_cpu_sw_state_rd(u32 cpu) in per_cpu_sw_state_rd() argument
61 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu))); in per_cpu_sw_state_rd()
62 return per_cpu(per_cpu_sw_state, cpu); in per_cpu_sw_state_rd()
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is …
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * x86_energy_perf_policy -- set the energy versus performance
7 * Copyright (c) 2010 - 2025 Intel Corporation.
30 #define OPTARG_NORMAL (INT_MAX - 1)
31 #define OPTARG_POWER (INT_MAX -
364 int cpu; validate_cpu_selected_set() local
379 int cpu = 0; parse_cmdline_cpu() local
680 get_msr(int cpu,int offset,unsigned long long * msr) get_msr() argument
704 put_msr(int cpu,int offset,unsigned long long new_msr) put_msr() argument
769 print_hwp_cap(int cpu,struct msr_hwp_cap * cap,char * str) print_hwp_cap() argument
777 read_hwp_cap(int cpu,struct msr_hwp_cap * cap,unsigned int msr_offset) read_hwp_cap() argument
789 print_hwp_request(int cpu,struct msr_hwp_request * h,char * str) print_hwp_request() argument
812 read_hwp_request(int cpu,struct msr_hwp_request * hwp_req,unsigned int msr_offset) read_hwp_request() argument
826 write_hwp_request(int cpu,struct msr_hwp_request * hwp_req,unsigned int msr_offset) write_hwp_request() argument
846 get_epb(int cpu) get_epb() argument
868 set_epb(int cpu,int val) set_epb() argument
892 print_cpu_msrs(int cpu) print_cpu_msrs() argument
959 update_cpufreq_scaling_freq(int is_max,int cpu,unsigned int ratio) update_cpufreq_scaling_freq() argument
993 update_sysfs(int cpu) update_sysfs() argument
1013 verify_hwp_req_self_consistency(int cpu,struct msr_hwp_request * req) verify_hwp_req_self_consistency() argument
1035 check_hwp_request_v_hwp_capabilities(int cpu,struct msr_hwp_request * req,struct msr_hwp_cap * cap) check_hwp_request_v_hwp_capabilities() argument
1077 update_hwp_request(int cpu) update_hwp_request() argument
1126 int cpu = first_cpu_in_pkg[pkg]; update_hwp_request_pkg() local
1167 enable_hwp_on_cpu(int cpu) enable_hwp_on_cpu() argument
1180 update_cpu_msrs(int cpu) update_cpu_msrs() argument
1231 get_pkg_num(int cpu) get_pkg_num() argument
1248 set_max_cpu_pkg_num(int cpu) set_max_cpu_pkg_num() argument
1270 mark_cpu_present(int cpu) mark_cpu_present() argument
[all...]
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is …
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/drivers/base/
H A Darch_topology.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arch specific cpu topology information
12 #include <linux/cpu.h>
67 int cpu; in topology_set_scale_freq_source() local
78 for_each_cpu(cpu, cpus) { in topology_set_scale_freq_source()
79 sfd = rcu_dereference(*per_cpu_ptr(&sft_data, cpu)); in topology_set_scale_freq_source()
82 if (!sfd || sfd->source != SCALE_FREQ_SOURCE_ARCH) { in topology_set_scale_freq_source()
83 rcu_assign_pointer(per_cpu(sft_data, cpu), data); in topology_set_scale_freq_source()
84 cpumask_set_cpu(cpu, &scale_freq_counters_mask); in topology_set_scale_freq_source()
98 int cpu; in topology_clear_scale_freq_source() local
[all …]
/linux/tools/testing/selftests/net/forwarding/
H A Dtsn_lib.sh2 # SPDX-License-Identifier: GPL-2.0
3 # Copyright 2021-2022 NXP
5 tc_testing_scripts_dir=$(dirname $0)/../../tc-testing/scripts
12 ISOCHRON_CPU=1
15 # https://github.com/vladimiroltean/tsn-scripts
16 # WARNING: isochron versions pre-1.0 are unstable,
28 local uds_address=$1
31 if ! [ -z "${uds_address}" ]; then
32 extra_args="${extra_args} -z ${uds_address}"
37 chrt -f 10 phc2sys -m \
[all …]
/linux/arch/powerpc/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
29 #include <linux/cpu.h>
76 /* State of each CPU during hotplug phases */
98 #define THREAD_GROUP_SHARE_L1 1
117 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
118 * the set its siblings that share the L1-cache.
123 * On some big-cores system, thread_group_l2_cache_map for each CPU
125 * L2-cache.
130 * On P10, thread_group_l3_cache_map for each CPU is equal to the
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …ata cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this c…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
28 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on…
[all …]
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
[all …]
/linux/arch/x86/xen/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/cpu.h>
10 #include <xen/hvc-console.h>
11 #include "xen-ops.h"
13 static DEFINE_PER_CPU(struct xen_common_irq, xen_resched_irq) = { .irq = -1 };
14 static DEFINE_PER_CPU(struct xen_common_irq, xen_callfunc_irq) = { .irq = -1 };
15 static DEFINE_PER_CPU(struct xen_common_irq, xen_callfuncsingle_irq) = { .irq = -1 };
16 static DEFINE_PER_CPU(struct xen_common_irq, xen_debug_irq) = { .irq = -1 };
32 void xen_smp_intr_free(unsigned int cpu) in xen_smp_intr_free() argument
34 kfree(per_cpu(xen_resched_irq, cpu).name); in xen_smp_intr_free()
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
[all …]
/linux/tools/power/cpupower/utils/helpers/
H A Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
24 if (fd == -1) in sysfs_read_file()
27 numread = read(fd, buf, buflen - 1); in sysfs_read_file()
28 if (numread < 1) { in sysfs_read_file()
40 * Detect whether a CPU is online
43 * 1 -> if CPU is online
44 * 0 -> if CPU is offline
47 int sysfs_is_cpu_online(unsigned int cpu) in sysfs_is_cpu_online() argument
57 snprintf(path, sizeof(path), PATH_TO_CPU "cpu%u", cpu); in sysfs_is_cpu_online()
[all …]
/linux/Documentation/core-api/
H A Dcpu_hotplug.rst2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
27 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
53 CPU maps
66 after a CPU is available for kernel scheduling and ready to receive
67 interrupts from devices. Its cleared when a CPU is brought down using
69 migrated to another target CPU.
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
21 …ata cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this c…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
[all …]
/linux/scripts/gdb/linux/
H A Dcpus.py4 # per-cpu tools
6 # Copyright (c) Siemens AG, 2011-2013
27 return gdb.selected_thread().num - 1
31 raise gdb.GdbError("Sorry, obtaining the current CPU is not yet "
35 def per_cpu(var_ptr, cpu): argument
36 if cpu == -1:
37 cpu = get_current_cpu()
40 "trap_block[{0}].__per_cpu_base".format(str(cpu)))
44 "__per_cpu_offset[{0}]".format(str(cpu)))
77 entry = -1
[all …]
/linux/arch/alpha/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * 2001-07-09 Phil Ezolt (Phillip.Ezolt@compaq.com)
31 #include <linux/cpu.h>
54 /* A collection of per-processor data. */
73 int smp_num_cpus = 1; /* Number that came online. */
78 * per-processor storage.
90 * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
95 cpu_data[cpuid].prof_counter = 1; in smp_setup_percpu_timer()
96 cpu_data[cpuid].prof_multiplier = 1; in smp_setup_percpu_timer()
110 printk("wait_boot_cpu_to_stop: FAILED on CPU %d, hanging now\n", cpuid); in wait_boot_cpu_to_stop()
[all …]
/linux/tools/power/cpupower/utils/
H A Dcpuidle-set.c1 // SPDX-License-Identifier: GPL-2.0
19 {"disable-by-latency", required_argument, NULL, 'D'},
20 {"enable-all", no_argument, NULL, 'E'},
29 int ret = 0, cont = 1, param = 0, disabled; in cmd_idle_set()
31 unsigned int cpu = 0, idlestate = 0, idlestates = 0; in cmd_idle_set() local
36 if (ret == -1) in cmd_idle_set()
46 param = -1; in cmd_idle_set()
61 param = -1; in cmd_idle_set()
74 param = -1; in cmd_idle_set()
80 case -1: in cmd_idle_set()
[all …]

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