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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drenesas,cpg-mstp-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
23 - enum:
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H A Drenesas,rz-cpg-clocks.txt1 * Renesas RZ/A1 Clock Pulse Generator (CPG)
3 The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
4 CPU and GPU clocks, and several fixed ratio dividers.
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
6 CPG Module Stop (MSTP) Clocks.
10 - compatible: Must be one of
11 - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
12 and "renesas,rz-cpg-clocks" as a fallback.
13 - reg: Base address and length of the memory resource used by the CPG
14 - clocks: References to possible parent clocks. Order must match clock modes
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H A Drenesas,r8a7778-cpg-clocks.txt1 * Renesas R8A7778 Clock Pulse Generator (CPG)
3 The CPG generates core clocks for the R8A7778. It includes two PLLs and
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
6 CPG Module Stop (MSTP) Clocks.
10 - compatible: Must be "renesas,r8a7778-cpg-clocks"
11 - reg: Base address and length of the memory resource used by the CPG
12 - #clock-cells: Must be 1
13 - clock-output-names: The names of the clocks. Supported clocks are
15 - #power-domain-cells: Must be 0
17 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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H A Drenesas,r8a7779-cpg-clocks.txt1 * Renesas R8A7779 Clock Pulse Generator (CPG)
3 The CPG generates core clocks for the R8A7779. It includes one PLL and
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
6 CPG Module Stop (MSTP) Clocks.
10 - compatible: Must be "renesas,r8a7779-cpg-clocks"
11 - reg: Base address and length of the memory resource used by the CPG
13 - clocks: Reference to the parent clock
14 - #clock-cells: Must be 1
15 - clock-output-names: The names of the clocks. Supported clocks are "plla",
17 - #power-domain-cells: Must be 0
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H A Drenesas,cpg-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
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/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr7s72100.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-binding
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H A Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dr8a73a4.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a15";
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H A Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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H A Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-binding
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