Lines Matching +full:cpg +full:- +full:mstp +full:- +full:clocks

1 * Renesas RZ/A1 Clock Pulse Generator (CPG)
3 The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
4 CPU and GPU clocks, and several fixed ratio dividers.
5 The CPG also provides a Clock Domain for SoC devices, in combination with the
6 CPG Module Stop (MSTP) Clocks.
10   - compatible: Must be one of
11     - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
12     and "renesas,rz-cpg-clocks" as a fallback.
13   - reg: Base address and length of the memory resource used by the CPG
14   - clocks: References to possible parent clocks. Order must match clock modes
16   - #clock-cells: Must be 1
17   - clock-output-names: The names of the clocks. Supported clocks are "pll",
19   - #power-domain-cells: Must be 0
21 SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
22 through an MSTP clock should refer to the CPG device node in their
23 "power-domains" property, as documented by the generic PM domain bindings in
28 --------
30   - CPG device node:
33 		#clock-cells = <1>;
34 		compatible = "renesas,r7s72100-cpg-clocks",
35 			     "renesas,rz-cpg-clocks";
37 		clocks = <&extal_clk>, <&usb_x1_clk>;
38 		clock-output-names = "pll", "i", "g";
39 		#power-domain-cells = <0>;
43   - CPG/MSTP Clock Domain member device node:
46 		compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
49 		interrupt-names = "tgi0a";
50 		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
51 		clock-names = "fck";
52 		power-domains = <&cpg_clocks>;