Lines Matching +full:cpg +full:- +full:mstp +full:- +full:clocks
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
26 - items:
27 - enum:
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
35 clocks: true
37 '#clock-cells':
40 clock-output-names: true
43 description: Board-specific settings of the MD_CK* bits on R-Mobile A1
48 '#power-domain-cells':
52 - compatible
53 - reg
54 - clocks
55 - '#clock-cells'
56 - clock-output-names
59 - if:
63 const: renesas,r8a73a4-cpg-clocks
66 clocks:
68 - description: extal1
69 - description: extal2
71 clock-output-names:
73 - const: main
74 - const: pll0
75 - const: pll1
76 - const: pll2
77 - const: pll2s
78 - const: pll2h
79 - const: z
80 - const: z2
81 - const: i
82 - const: m3
83 - const: b
84 - const: m1
85 - const: m2
86 - const: zx
87 - const: zs
88 - const: hp
90 - if:
94 const: renesas,r8a7740-cpg-clocks
97 clocks:
99 - description: extal1
100 - description: extal2
101 - description: extalr
103 clock-output-names:
105 - const: system
106 - const: pllc0
107 - const: pllc1
108 - const: pllc2
109 - const: r
110 - const: usb24s
111 - const: i
112 - const: zg
113 - const: b
114 - const: m1
115 - const: hp
116 - const: hpp
117 - const: usbp
118 - const: s
119 - const: zb
120 - const: m3
121 - const: cp
124 - renesas,mode
126 - if:
130 const: renesas,r8a7778-cpg-clocks
133 clocks:
136 clock-output-names:
138 - const: plla
139 - const: pllb
140 - const: b
141 - const: out
142 - const: p
143 - const: s
144 - const: s1
146 - if:
150 const: renesas,r8a7779-cpg-clocks
153 clocks:
156 clock-output-names:
158 - const: plla
159 - const: z
160 - const: zs
161 - const: s
162 - const: s1
163 - const: p
164 - const: b
165 - const: out
167 - if:
171 const: renesas,r7s72100-cpg-clocks
174 clocks:
176 - description: extal1
177 - description: usb_x1
179 clock-output-names:
181 - const: pll
182 - const: i
183 - const: g
185 - if:
189 const: renesas,sh73a0-cpg-clocks
192 clocks:
194 - description: extal1
195 - description: extal2
197 clock-output-names:
199 - const: main
200 - const: pll0
201 - const: pll1
202 - const: pll2
203 - const: pll3
204 - const: dsi0phy
205 - const: dsi1phy
206 - const: zg
207 - const: m3
208 - const: b
209 - const: m1
210 - const: m2
211 - const: z
212 - const: zx
213 - const: hp
215 - if:
220 - renesas,r8a7778-cpg-clocks
221 - renesas,r8a7779-cpg-clocks
222 - renesas,rz-cpg-clocks
225 - '#power-domain-cells'
230 - |
231 #include <dt-bindings/clock/r8a7740-clock.h>
233 compatible = "renesas,r8a7740-cpg-clocks";
235 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
236 #clock-cells = <1>;
237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",