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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a53";
[all …]
H A Dmt6797.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/clock/mt6797-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/mt6797-pinfunc.h>
14 interrupt-parent = <&sysirq>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <1>;
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/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dsilicon-errata.txt1 SPDX-License-Identifier: GPL-2.0
3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
15 ---------------------------------------------------------------------
16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯
30 ---------------------------------------------------------------------
55 相應的內核配置（Kconfig）選項被加在 “內核特性（Kernel Features）”->
66 +----------------+-----------------+-----------------+-------------------------+
67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
69 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dsilicon-errata.txt1 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arch/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-a4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "amlogic-a4-common.dtsi"
7 #include <dt-bindings/power/amlogic,a4-pwrc.h>
10 #address-cells = <2>;
11 #size-cells = <0>;
15 compatible = "arm,cortex-a53";
17 enable-method = "psci";
22 compatible = "arm,cortex-a53";
24 enable-method = "psci";
29 compatible = "arm,cortex-a53";
[all …]
H A Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
19 cpu-map {
[all …]
H A Dmeson-g12a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-g12.dtsi"
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
17 compatible = "arm,cortex-a53";
19 enable-method = "psci";
20 next-level-cache = <&l2>;
21 #cooling-cells = <2>;
26 compatible = "arm,cortex-a53";
28 enable-method = "psci";
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/linux/arch/arm64/boot/dts/intel/
H A Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
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/linux/arch/arm64/boot/dts/freescale/
H A Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
[all …]
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
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/linux/arch/arm64/boot/dts/realtek/
H A Drtd1296.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2017-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
H A Drtd1295.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
[all …]
H A Drtd1395.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
14 #address-cells = <2>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
26 compatible = "arm,cortex-a53";
28 next-level-cache = <&l2>;
33 compatible = "arm,cortex-a53";
35 next-level-cache = <&l2>;
40 compatible = "arm,cortex-a53";
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
34 interrupt-affinity = <&cpu0>,
42 arm-a73-pmu {
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/linux/arch/arm64/boot/dts/arm/
H A Djuno-r2.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
H A Djuno.dts4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
[all …]
H A Djuno-r1.dts9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
H A Dvexpress-v2f-1xv7-ca53x2.dts1 // SPDX-License-Identifier: GPL-2.0
6 * V2F-1XV7
8 * Cortex-A53 (2 cores) Soft Macrocell Model
10 * HBI-0247C
13 /dts-v1/;
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "arm/arm/vexpress-v2m-rs1.dtsi"
19 model = "V2F-1XV7 Cortex-A53x2 SMM";
22 compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
23 interrupt-parent = <&gic>;
[all …]
/linux/tools/perf/pmu-events/arch/arm64/
H A Dmapfile.csv10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd020,v1,arm/cortex-a34,core
16 0x00000000410fd030,v1,arm/cortex-a53,core
17 0x00000000420f1000,v1,arm/cortex-a53,cor
[all...]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
[all …]
/linux/arch/arm64/boot/dts/airoha/
H A Den7581.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 interrupt-parent = <&gic>;
8 #address-cells = <2>;
9 #size-cells = <2>;
11 reserved-memory {
12 #address-cells = <2>;
13 #size-cells = <2>;
16 npu-binary@84000000 {
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
[all …]
/linux/arch/arm64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
279 ARM 64-bit (AArch64) Linux support.
287 # required due to use of the -Zfixed-x18 flag.
290 # -Zsanitizer=shadow-call-stack flag.
300 depends on $(cc-option,-fpatchable-function-entry=2)
326 # VA_BITS - PAGE_SHIFT - 3
404 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
409 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
459 at stage-2.
467 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
[all …]

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