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/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
19 #include "pinctrl-samsung.h"
20 #include "pinctrl-exynos.h"
53 * Bank type for non-alive type. Bit fields:
71 * Bank type for non-alive type. Bit fields:
80 * Bank type for non-alive type. Bit fields:
91 /* pin banks of exynos2200 pin-controller - ALIVE */
103 /* pin banks of exynos2200 pin-controller - CMGP */
130 /* pin banks of exynos2200 pin-controller - HSI1 */
[all …]
H A Dpinctrl-exynos-arm.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
35 /* Retention control for S5PV210 are located at the end of clock controller */
49 unsigned int *pud_val = drvdata->pud_val; in s5pv210_pud_value_init()
58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable()
69 const struct samsung_retention_data *data) in s5pv210_retention_init() argument
75 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); in s5pv210_retention_init()
77 return ERR_PTR(-ENOMEM); in s5pv210_retention_init()
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H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
90 * Samsung GPIO controller groups all the available pins into banks. The pins
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
[all …]
/linux/drivers/input/joystick/
H A Dxpad.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2002 Marko Friedemann <mfr@bmx-chemnitz.de>
16 * - information from http://euc.jp/periphs/xbox-controller.ja.html
17 * - th
585 const u8 *data; global() member
739 u8 data[XPAD_PKT_LEN]; global() member
808 xpad_process_packet(struct usb_xpad * xpad,u16 cmd,unsigned char * data) xpad_process_packet() argument
880 xpad360_process_packet(struct usb_xpad * xpad,struct input_dev * dev,u16 cmd,unsigned char * data) xpad360_process_packet() argument
1008 xpad360w_process_packet(struct usb_xpad * xpad,u16 cmd,unsigned char * data) xpad360w_process_packet() argument
1043 xpadone_process_packet(struct usb_xpad * xpad,u16 cmd,unsigned char * data,u32 len) xpadone_process_packet() argument
1538 xpad_play_effect(struct input_dev * dev,void * data,struct ff_effect * effect) xpad_play_effect() argument
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-ep9301.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linusw@kernel.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
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/linux/drivers/usb/musb/
H A Dux500_dma.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright (C) 2011 ST-Ericsson SA
18 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/usb-musb-ux500.h>
32 struct ux500_dma_controller *controller; member
43 struct dma_controller controller; member
54 struct ux500_dma_channel *ux500_channel = channel->private_data; in ux500_dma_callback()
55 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; in ux500_dma_callback()
56 struct musb *musb = hw_ep->musb; in ux500_dma_callback()
59 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
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/linux/Documentation/driver-api/usb/
H A Dwriting_musb_glue_layer.rst12 use Universal Host Controller Interface (UHCI) or Open Host Controller
15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
42 Linux USB stack is a layered architecture in which the MUSB controller
43 hardware sits at the lowest. The MUSB controller driver abstract the
44 MUSB controller hardware to the Linux USB stack::
46 ------------------------
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/linux/include/linux/
H A Dmhi.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
10 #include <linux/dma-direction.h>
17 #include <linux/device-id/mhi.h>
28 * enum mhi_callback - MHI callback
30 * @MHI_CB_PENDING_DATA: New data available for client to process
52 * enum mhi_flags - Transfer flags
64 * enum mhi_device_type - Device types
65 * @MHI_DEVICE_XFER: Handles data transfer
74 * enum mhi_ch_type - Channel types
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/linux/Documentation/devicetree/bindings/media/
H A Dmicrochip,csi2dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip CSI2 Demux Controller (CSI2DC)
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 CSI2DC - Camera Serial Interface 2 Demux Controller
15 CSI2DC is a hardware block that receives incoming data from either from an
17 It filters IDI packets based on their data type and virtual channel
20 controller.
22 CSI2DC can act a simple bypass bridge if the incoming data is coming from
[all …]
/linux/Documentation/wmi/devices/
H A Dmsi-wmi-platform.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 MSI WMI Platform Features driver (msi-wmi-platform)
11 by the embedded controller, with the ACPI firmware exposing a standard ACPI WMI interface on top
12 of the embedded controller interface.
18 data using the `bmfdec <https://github.com/pali/bmfdec>`_ utility:
24 guid("{ABBC0F60-8EA1-11d1-00A0-C90629100000}")]
26 [WmiDataId(1), read, write, Description("16 bytes of data")] uint8 Bytes[16];
31 guid("{ABBC0F63-8EA1-11d1-00A0-C90629100000}")]
33 [WmiDataId(1), read, write, Description("32 bytes of data")] uint8 Bytes[32];
38 guid("{ABBC0F6E-8EA1-11d1-00A0-C90629100000}")]
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/linux/drivers/mtd/nand/raw/
H A Dtechnologic-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Technologic Systems TS72xx NAND controller driver
33 struct nand_controller controller; member
47 switch (chip->ecc.engine_type) { in ts72xx_nand_attach_chip()
49 return -EINVAL; in ts72xx_nand_attach_chip()
51 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) in ts72xx_nand_attach_chip()
52 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
53 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in ts72xx_nand_attach_chip()
62 struct ts72xx_nand_data *data = chip_to_ts72xx(chip); in ts72xx_nand_ctrl() local
63 unsigned char bits = ioread8(data->ctrl) & ~GENMASK(2, 0); in ts72xx_nand_ctrl()
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H A Dcs553x_nand.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This is a device driver for the NAND flash controller found on
11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
34 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
54 /* Registers within the NAND flash controller BAR -- memory mapped */
56 #define MM_NAND_CTL 0x800 /* Any even address 0x800-0x80e */
57 #define MM_NAND_IO 0x801 /* Any odd address 0x801-0x80f */
65 /* Registers within the NAND flash controller BAR -- I/O mapped */
98 to_cs553x(struct nand_controller *controller) in to_cs553x() argument
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/linux/drivers/reset/
H A Dreset-scmi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2021 ARM Ltd.
11 #include <linux/reset-controller.h>
17 * struct scmi_reset_data - reset controller information structure
18 * @rcdev: reset controller entity
19 * @ph: ARM SCMI protocol handle used for communication with system controller
27 #define to_scmi_handle(p) (to_scmi_reset_data(p)->ph)
30 * scmi_reset_assert() - assert device reset
31 * @rcdev: reset controller entity
44 return reset_ops->assert(ph, id); in scmi_reset_assert()
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H A Dreset-ti-sci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Texas Instrument's System Control Interface (TI-SCI) reset driver
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
14 #include <linux/reset-controller.h>
18 * struct ti_sci_reset_control - reset control structure
19 * @dev_id: SoC-specific device identifier
21 * @lock: synchronize reset_mask read-modify-writes
30 * struct ti_sci_reset_data - reset controller information structure
31 * @rcdev: reset controller entity
32 * @dev: reset controller device pointer
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/linux/drivers/edac/
H A Dmpc85xx_edac.c2 * Freescale MPC85xx Memory Controller kernel module
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
51 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check()
54 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check()
58 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
66 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check()
68 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
70 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check()
72 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
74 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
[all …]
H A Daltera_edac.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
10 #include <linux/arm-smccc.h>
14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
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H A Dsynopsys_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
19 /* Number of cs_rows needed per memory controller */
22 /* Number of channels per memory controller */
33 /* Synopsys DDR memory controller registers that are relevant to ECC */
43 /* ECC data[31:0] register */
94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
268 * struct ecc_error_info - ECC error log information.
273 * @data: Data causing the error.
282 u32 data; member
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/linux/drivers/dma/
H A Dacpi-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ACPI helpers for DMA request / controller
5 * Based on of-dma.c
15 #include <linux/dma-mapping.h>
32 * acpi_dma_parse_resource_group - match device and parse resource group
35 * @adma: struct acpi_dma of the given DMA controller
53 if (grp->shared_info_length != sizeof(struct acpi_csrt_shared_info)) in acpi_dma_parse_resource_group()
54 return -ENODEV; in acpi_dma_parse_resource_group()
62 if (resource_type(rentry->res) == IORESOURCE_MEM) in acpi_dma_parse_resource_group()
63 mem = rentry->res->start; in acpi_dma_parse_resource_group()
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H A Dof-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree helpers for DMA request / controller
7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
24 * of_dma_find_controller - Get a DMA controller in DT DMA helpers list
27 * Finds a DMA controller with matching device node and number for dma cells
29 * to the DMA data stored is returned. A NULL pointer is returned if no match is
37 if (ofdma->of_node == dma_spec->np) in of_dma_find_controller()
40 pr_debug("%s: can't find DMA controller %pOF\n", __func__, in of_dma_find_controller()
41 dma_spec->np); in of_dma_find_controller()
47 * of_dma_router_xlate - translation function for router devices
[all …]
/linux/drivers/pinctrl/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
33 * controller
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
40 * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
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/linux/drivers/spi/
H A Dspi-stm32.c1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
202 #define STM32_SPI_HOST_MODE(stm32_spi) (!(stm32_spi)->device_mode)
203 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
210 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
222 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
231 * @rx: SPI RX data register
232 * @tx: SPI TX data register
[all …]
/linux/drivers/slimbus/
H A Dslimbus.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2011-2017, The Linux Foundation
48 /* Data channel management messages */
91 * struct slim_framer - Represents SLIMbus framer.
92 * Every controller may have multiple framers. There is 1 active framer device
94 * Manager is responsible for framer hand-over.
111 * struct slim_msg_txn - Message to be sent by the controller.
120 * (relevant for message-codes involving read operation)
152 * enum slim_clk_state: SLIMbus controller's clock state used internally for
158 * @SLIM_CLK_PAUSED: SLIMbus controller clock has paused.
[all …]
/linux/include/linux/spi/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/device-id/acpi.h>
16 #include <linux/device-id/of.h>
17 #include <linux/device-id/spi.h>
28 /* Max no. of data lanes supported per spi device */
43 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers,
49 * struct spi_statistics - statistics for spi transfers
50 * @syncp: seqcount to protect members in this struct for per-cpu update
51 * on 32-bit systems
53 * @messages: number of spi-messages handled
[all …]
/linux/drivers/mtd/nand/
H A Dqpic_common.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
16 #include <linux/mtd/nand-qpic-common.h>
19 * qcom_free_bam_transaction() - Frees the BAM transaction memory
20 * @nandc: qpic nand controller
26 struct bam_transaction *bam_txn = nandc->bam_txn; in qcom_free_bam_transaction()
33 * qcom_alloc_bam_transaction() - allocate BAM transaction
34 * @nandc: qpic nand controller
43 unsigned int num_cw = nandc->max_cwperpage; in qcom_alloc_bam_transaction()
48 ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) + in qcom_alloc_bam_transaction()
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/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hitachi HD44780 Character LCD Controller
10 - Geert Uytterhoeven <geert@linux-m68k.org>
13 The Hitachi HD44780 Character LCD Controller is commonly used on character
15 interface, which can be used in either 4-bit or 8-bit mode. By using a
24 data-gpios:
26 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
27 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
[all …]

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