Lines Matching +full:controller +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
19 /* Number of cs_rows needed per memory controller */
22 /* Number of channels per memory controller */
33 /* Synopsys DDR memory controller registers that are relevant to ECC */
43 /* ECC data[31:0] register */
94 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
268 * struct ecc_error_info - ECC error log information.
273 * @data: Data causing the error.
282 u32 data; member
288 * struct synps_ecc_status - ECC status information to report.
302 * struct synps_edac_priv - DDR memory controller private instance data.
303 * @baseaddr: Base address of the DDR controller.
307 * @p_data: Platform data.
310 * @poison_addr: Data poison address.
342 * struct synps_platform_data - synps platform data structure.
362 * zynq_get_error_info - Get the current ECC error info.
363 * @priv: DDR memory controller private instance data.
373 base = priv->baseaddr; in zynq_get_error_info()
374 p = &priv->stat; in zynq_get_error_info()
380 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
381 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
384 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
387 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
389 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
390 p->ceinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
391 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
392 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in zynq_get_error_info()
393 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, in zynq_get_error_info()
394 p->ceinfo.data); in zynq_get_error_info()
399 if (!(p->ue_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
403 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
404 p->ueinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
405 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
406 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in zynq_get_error_info()
418 * zynqmp_get_mem_info - Get the current memory info.
419 * @priv: DDR memory controller private instance data.
427 linear_addr = priv->poison_addr; in zynqmp_get_mem_info()
429 linear_addr = linear_addr - SZ_32G + SZ_2G; in zynqmp_get_mem_info()
436 * zynqmp_get_error_info - Get the current ECC error info.
437 * @priv: DDR memory controller private instance data.
448 base = priv->baseaddr; in zynqmp_get_error_info()
449 p = &priv->stat; in zynqmp_get_error_info()
452 p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; in zynqmp_get_error_info()
453 p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; in zynqmp_get_error_info()
454 if (!p->ce_cnt) in zynqmp_get_error_info()
461 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); in zynqmp_get_error_info()
464 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
466 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
468 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
470 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
471 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); in zynqmp_get_error_info()
476 if (!p->ue_cnt) in zynqmp_get_error_info()
480 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
482 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
484 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
486 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
487 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); in zynqmp_get_error_info()
489 spin_lock_irqsave(&priv->reglock, flags); in zynqmp_get_error_info()
496 spin_unlock_irqrestore(&priv->reglock, flags); in zynqmp_get_error_info()
502 * handle_error - Handle Correctable and Uncorrectable errors.
503 * @mci: EDAC memory controller instance.
510 struct synps_edac_priv *priv = mci->pvt_info; in handle_error()
513 if (p->ce_cnt) { in handle_error()
514 pinf = &p->ceinfo; in handle_error()
515 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
516 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
517 …CC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x", in handle_error()
518 "CE", pinf->row, pinf->bank, in handle_error()
519 pinf->bankgrpnr, pinf->blknr, in handle_error()
520 pinf->bitpos, pinf->data); in handle_error()
522 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
523 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", in handle_error()
524 "CE", pinf->row, pinf->bank, pinf->col, in handle_error()
525 pinf->bitpos, pinf->data); in handle_error()
529 p->ce_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
530 priv->message, ""); in handle_error()
533 if (p->ue_cnt) { in handle_error()
534 pinf = &p->ueinfo; in handle_error()
535 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
536 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
538 "UE", pinf->row, pinf->bank, in handle_error()
539 pinf->bankgrpnr, pinf->blknr); in handle_error()
541 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
543 "UE", pinf->row, pinf->bank, pinf->col); in handle_error()
547 p->ue_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
548 priv->message, ""); in handle_error()
559 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in enable_intr()
561 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); in enable_intr()
566 spin_lock_irqsave(&priv->reglock, flags); in enable_intr()
569 priv->baseaddr + ECC_CLR_OFST); in enable_intr()
571 spin_unlock_irqrestore(&priv->reglock, flags); in enable_intr()
579 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in disable_intr()
581 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); in disable_intr()
586 spin_lock_irqsave(&priv->reglock, flags); in disable_intr()
588 writel(0, priv->baseaddr + ECC_CLR_OFST); in disable_intr()
590 spin_unlock_irqrestore(&priv->reglock, flags); in disable_intr()
594 * intr_handler - Interrupt Handler for ECC interrupts.
607 priv = mci->pvt_info; in intr_handler()
608 p_data = priv->p_data; in intr_handler()
611 * v3.0 of the controller has the ce/ue bits cleared automatically, in intr_handler()
614 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { in intr_handler()
615 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
621 status = p_data->get_error_info(priv); in intr_handler()
625 priv->ce_cnt += priv->stat.ce_cnt; in intr_handler()
626 priv->ue_cnt += priv->stat.ue_cnt; in intr_handler()
627 handle_error(mci, &priv->stat); in intr_handler()
630 priv->ce_cnt, priv->ue_cnt); in intr_handler()
631 /* v3.0 of the controller does not have this register */ in intr_handler()
632 if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) in intr_handler()
633 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
639 * check_errors - Check controller for ECC errors.
640 * @mci: EDAC memory controller instance.
650 priv = mci->pvt_info; in check_errors()
651 p_data = priv->p_data; in check_errors()
653 status = p_data->get_error_info(priv); in check_errors()
657 priv->ce_cnt += priv->stat.ce_cnt; in check_errors()
658 priv->ue_cnt += priv->stat.ue_cnt; in check_errors()
659 handle_error(mci, &priv->stat); in check_errors()
662 priv->ce_cnt, priv->ue_cnt); in check_errors()
666 * zynq_get_dtype - Return the controller memory width.
667 * @base: DDR memory controller base address.
669 * Get the EDAC device type width appropriate for the current controller
697 * zynqmp_get_dtype - Return the controller memory width.
698 * @base: DDR memory controller base address.
700 * Get the EDAC device type width appropriate for the current controller
734 if (priv->p_data->platform == ZYNQ) { in get_ecc_state()
735 dt = zynq_get_dtype(priv->baseaddr); in get_ecc_state()
739 ecctype = readl(priv->baseaddr + SCRUB_OFST) & SCRUB_MODE_MASK; in get_ecc_state()
742 writel(clearval, priv->baseaddr + ECC_CTRL_OFST); in get_ecc_state()
743 writel(0x0, priv->baseaddr + ECC_CTRL_OFST); in get_ecc_state()
747 dt = zynqmp_get_dtype(priv->baseaddr); in get_ecc_state()
751 ecctype = readl(priv->baseaddr + ECC_CFG0_OFST) & SCRUB_MODE_MASK; in get_ecc_state()
754 clearval = readl(priv->baseaddr + ECC_CLR_OFST) | in get_ecc_state()
757 writel(clearval, priv->baseaddr + ECC_CLR_OFST); in get_ecc_state()
766 * get_memsize - Read the size of the attached memory device.
780 * zynq_get_mtype - Return the controller memory type.
783 * Get the EDAC memory type appropriate for the current controller
804 * zynqmp_get_mtype - Returns controller memory type.
807 * Get the EDAC memory type appropriate for the current controller
832 * init_csrows - Initialize the csrow data.
833 * @mci: EDAC memory controller instance.
836 * controller instance.
840 struct synps_edac_priv *priv = mci->pvt_info; in init_csrows()
847 p_data = priv->p_data; in init_csrows()
849 for (row = 0; row < mci->nr_csrows; row++) { in init_csrows()
850 csi = mci->csrows[row]; in init_csrows()
853 for (j = 0; j < csi->nr_channels; j++) { in init_csrows()
854 dimm = csi->channels[j]->dimm; in init_csrows()
855 dimm->edac_mode = EDAC_SECDED; in init_csrows()
856 dimm->mtype = p_data->get_mtype(priv->baseaddr); in init_csrows()
857 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; in init_csrows()
858 dimm->grain = SYNPS_EDAC_ERR_GRAIN; in init_csrows()
859 dimm->dtype = p_data->get_dtype(priv->baseaddr); in init_csrows()
865 * mc_init - Initialize one driver instance.
866 * @mci: EDAC memory controller instance.
869 * Perform initialization of the EDAC memory controller instance and
870 * related driver-private data associated with the memory controller the
877 mci->pdev = &pdev->dev; in mc_init()
878 priv = mci->pvt_info; in mc_init()
881 /* Initialize controller capabilities and configuration */ in mc_init()
882 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; in mc_init()
883 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in mc_init()
884 mci->scrub_cap = SCRUB_HW_SRC; in mc_init()
885 mci->scrub_mode = SCRUB_NONE; in mc_init()
887 mci->edac_cap = EDAC_FLAG_SECDED; in mc_init()
888 mci->ctl_name = "synps_ddr_controller"; in mc_init()
889 mci->dev_name = SYNPS_EDAC_MOD_STRING; in mc_init()
890 mci->mod_name = SYNPS_EDAC_MOD_VER; in mc_init()
892 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_init()
896 mci->edac_check = check_errors; in mc_init()
899 mci->ctl_page_to_phys = NULL; in mc_init()
907 struct synps_edac_priv *priv = mci->pvt_info; in setup_irq()
917 ret = devm_request_irq(&pdev->dev, irq, intr_handler, in setup_irq()
918 0, dev_name(&pdev->dev), mci); in setup_irq()
967 .compatible = "xlnx,zynq-ddrc-a05",
968 .data = (void *)&zynq_edac_def
971 .compatible = "xlnx,zynqmp-ddrc-2.40a",
972 .data = (void *)&zynqmp_edac_def
975 .compatible = "snps,ddrc-3.80a",
976 .data = (void *)&synopsys_edac_def
989 * ddr_poison_setup - Update poison registers.
990 * @priv: DDR memory controller private instance data.
1002 p_data = priv->p_data; in ddr_poison_setup()
1004 if (p_data->get_mem_info) in ddr_poison_setup()
1005 hif_addr = p_data->get_mem_info(priv); in ddr_poison_setup()
1007 hif_addr = priv->poison_addr >> 3; in ddr_poison_setup()
1010 if (priv->row_shift[index]) in ddr_poison_setup()
1011 row |= (((hif_addr >> priv->row_shift[index]) & in ddr_poison_setup()
1018 if (priv->col_shift[index] || index < 3) in ddr_poison_setup()
1019 col |= (((hif_addr >> priv->col_shift[index]) & in ddr_poison_setup()
1026 if (priv->bank_shift[index]) in ddr_poison_setup()
1027 bank |= (((hif_addr >> priv->bank_shift[index]) & in ddr_poison_setup()
1034 if (priv->bankgrp_shift[index]) in ddr_poison_setup()
1035 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) in ddr_poison_setup()
1041 if (priv->rank_shift[0]) in ddr_poison_setup()
1042 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); in ddr_poison_setup()
1046 writel(regval, priv->baseaddr + ECC_POISON0_OFST); in ddr_poison_setup()
1051 writel(regval, priv->baseaddr + ECC_POISON1_OFST); in ddr_poison_setup()
1056 char *data) in inject_data_error_show() argument
1059 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_show()
1061 return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r" in inject_data_error_show()
1063 readl(priv->baseaddr + ECC_POISON0_OFST), in inject_data_error_show()
1064 readl(priv->baseaddr + ECC_POISON1_OFST), in inject_data_error_show()
1065 priv->poison_addr); in inject_data_error_show()
1070 const char *data, size_t count) in inject_data_error_store() argument
1073 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_store()
1075 if (kstrtoul(data, 0, &priv->poison_addr)) in inject_data_error_store()
1076 return -EINVAL; in inject_data_error_store()
1085 char *data) in inject_data_poison_show() argument
1088 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_show()
1090 return sprintf(data, "Data Poisoning: %s\n\r", in inject_data_poison_show()
1091 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) in inject_data_poison_show()
1097 const char *data, size_t count) in inject_data_poison_store() argument
1100 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_store()
1102 writel(0, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1103 if (strncmp(data, "CE", 2) == 0) in inject_data_poison_store()
1104 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1106 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1107 writel(1, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1119 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); in edac_create_sysfs_attributes()
1122 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); in edac_create_sysfs_attributes()
1130 device_remove_file(&mci->dev, &dev_attr_inject_data_error); in edac_remove_sysfs_attributes()
1131 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); in edac_remove_sysfs_attributes()
1139 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; in setup_row_address_map()
1140 priv->row_shift[1] = ((addrmap[5] >> 8) & in setup_row_address_map()
1146 priv->row_shift[index] = addrmap_row_b2_10 + in setup_row_address_map()
1150 priv->row_shift[2] = (addrmap[9] & in setup_row_address_map()
1152 priv->row_shift[3] = ((addrmap[9] >> 8) & in setup_row_address_map()
1154 priv->row_shift[4] = ((addrmap[9] >> 16) & in setup_row_address_map()
1156 priv->row_shift[5] = ((addrmap[9] >> 24) & in setup_row_address_map()
1158 priv->row_shift[6] = (addrmap[10] & in setup_row_address_map()
1160 priv->row_shift[7] = ((addrmap[10] >> 8) & in setup_row_address_map()
1162 priv->row_shift[8] = ((addrmap[10] >> 16) & in setup_row_address_map()
1164 priv->row_shift[9] = ((addrmap[10] >> 24) & in setup_row_address_map()
1166 priv->row_shift[10] = (addrmap[11] & in setup_row_address_map()
1170 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1173 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1176 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1179 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1182 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1185 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1188 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1198 memtype = readl(priv->baseaddr + CTRL_OFST); in setup_column_address_map()
1201 priv->col_shift[0] = 0; in setup_column_address_map()
1202 priv->col_shift[1] = 1; in setup_column_address_map()
1203 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; in setup_column_address_map()
1204 priv->col_shift[3] = ((addrmap[2] >> 8) & in setup_column_address_map()
1206 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1209 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1212 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == in setup_column_address_map()
1215 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1218 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1221 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1226 priv->col_shift[10] = ((addrmap[4] & in setup_column_address_map()
1230 priv->col_shift[11] = (((addrmap[4] >> 8) & in setup_column_address_map()
1235 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1239 priv->col_shift[13] = (((addrmap[4] >> 8) & in setup_column_address_map()
1246 priv->col_shift[10] = (((addrmap[3] >> 24) & in setup_column_address_map()
1250 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1255 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1259 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1266 priv->col_shift[10] = (((addrmap[3] >> 16) & in setup_column_address_map()
1270 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1274 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1279 priv->col_shift[11] = (((addrmap[3] >> 16) & in setup_column_address_map()
1283 priv->col_shift[13] = (((addrmap[3] >> 24) & in setup_column_address_map()
1291 for (index = 9; index > width; index--) { in setup_column_address_map()
1292 priv->col_shift[index] = priv->col_shift[index - width]; in setup_column_address_map()
1293 priv->col_shift[index - width] = 0; in setup_column_address_map()
1301 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; in setup_bank_address_map()
1302 priv->bank_shift[1] = ((addrmap[1] >> 8) & in setup_bank_address_map()
1304 priv->bank_shift[2] = (((addrmap[1] >> 16) & in setup_bank_address_map()
1313 priv->bankgrp_shift[0] = (addrmap[8] & in setup_bg_address_map()
1315 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == in setup_bg_address_map()
1323 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == in setup_rank_address_map()
1329 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1330 * @priv: DDR memory controller private instance data.
1345 addrmap[index] = readl(priv->baseaddr + addrmap_offset); in setup_address_map()
1361 * mc_probe - Check controller and bind driver.
1364 * Probe a specific controller instance for binding with the driver.
1366 * Return: 0 if the controller instance was successfully bound to the
1382 p_data = of_device_get_match_data(&pdev->dev); in mc_probe()
1384 return -ENODEV; in mc_probe()
1399 return -ENOMEM; in mc_probe()
1402 priv = mci->pvt_info; in mc_probe()
1403 priv->baseaddr = baseaddr; in mc_probe()
1404 priv->p_data = p_data; in mc_probe()
1407 rc = -ENODEV; in mc_probe()
1411 spin_lock_init(&priv->reglock); in mc_probe()
1415 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_probe()
1429 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { in mc_probe()
1438 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_probe()
1446 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) in mc_probe()
1458 * mc_remove - Unbind driver from controller.
1466 struct synps_edac_priv *priv = mci->pvt_info; in mc_remove()
1468 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_remove()
1472 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) in mc_remove()
1476 edac_mc_del_mc(&pdev->dev); in mc_remove()
1482 .name = "synopsys-edac",