| /linux/Documentation/driver-api/rapidio/ |
| H A D | rapidio.rst | 5 The RapidIO standard is a packet-based fabric interconnect standard designed for
8 is publicly available for download from the RTA web-site [1].
17 into the kernel similarly to other buses by defining RapidIO-specific device and
21 architecture-specific interfaces that provide support for common RapidIO
33 ---------------
38 by a rio_mport data structure. This structure contains master port specific
43 RapidIO master ports are serviced by subsystem specific mport device drivers
46 includes rio_ops data structure which contains pointers to hardware specific
50 ----------
54 structure. Devices form one global device list and per-network device lists
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| /linux/drivers/staging/media/deprecated/atmel/ |
| H A D | atmel-isc-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
72 /* ISC Clock Configuration Register */
137 /* ISC White Balance Configuration Register */
155 /* ISC Color Filter Array Configuration Register */
226 /* Offset for CSC register specific to sama5d2 product */
228 /* Offset for CSC register specific to sama7g5 product */
252 /* Offset for CBC register specific to sama5d2 product */
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| H A D | atmel-isc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
13 #include <linux/clk-provider.h>
16 #include <media/v4l2-ctrls.h>
17 #include <media/v4l2-device.h>
18 #include <media/videobuf2-dma-contig.h>
57 * struct isc_format - ISC media bus format information
97 * struct fmt_config - ISC format configuration and internal pipeline
98 This structure represents the internal configuration
102 configuration.
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| /linux/drivers/media/platform/microchip/ |
| H A D | microchip-isc-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* ISC Parallel Front End Configuration 0 Register */
44 /* ISC Parallel Front End Configuration 1 Register */
52 /* ISC Parallel Front End Configuration 2 Register */
72 /* ISC Clock Configuration Register */
137 /* ISC White Balance Configuration Register */
155 /* ISC Color Filter Array Configuration Register */
226 /* Offset for CSC register specific to sama5d2 product */
228 /* Offset for CSC register specific to sama7g5 product */
252 /* Offset for CBC register specific to sama5d2 product */
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| H A D | microchip-isc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
13 #include <linux/clk-provider.h>
16 #include <media/v4l2-ctrls.h>
17 #include <media/v4l2-device.h>
18 #include <media/videobuf2-dma-contig.h>
57 * struct isc_format - ISC media bus format information
98 * struct fmt_config - ISC format configuration and internal pipeline
99 This structure represents the internal configuration
103 configuration.
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| /linux/include/linux/ |
| H A D | rio_drv.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 * rio_local_read_config_32 - Read 32 bits from local configuration space
48 * @offset: Offset into local configuration space
52 * device's configuration space.
61 * rio_local_write_config_32 - Write 32 bits to local configuration space
63 * @offset: Offset into local configuration space
67 * device's configuration space.
76 * rio_local_read_config_16 - Read 16 bits from local configuration space
78 * @offset: Offset into local configuration space
82 * device's configuration space.
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
15 used for a specific device or function. This node represents both mux and config
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
28 imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
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| H A D | marvell,mvebu-pinctrl.txt | 3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
4 (mpp) to a specific function. For each SoC family there is a SoC specific
7 Please refer to pinctrl-bindings.txt in this directory for details of the
9 phrase "pin configuration node".
11 A Marvell SoC pin configuration node is a node of a group of pins which can
12 be used for a specific device or function. Each node requires one or more
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
19 Required properties for pin configuration node:
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
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| H A D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
8 Hardware modules whose signals are affected by pin configuration are
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
15 need to reconfigure pins at run-time, for example to tri-state pins when the
22 configuration used by those states.
26 driver loads. This would allow representing a board's static pin configuration
31 they require certain specific named states for dynamic pin configuration.
37 property exists to define the pin configuration. Each state may also be
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| /linux/Documentation/arch/arm/samsung/ |
| H A D | gpio.rst | 6 ------------
9 specific calls provided alongside the drivers/gpio core.
13 -------------------
16 specific calls for the items that require Samsung specific handling, such
17 as pin special-function or pull resistor control.
22 PIN configuration
23 -----------------
25 Pin configuration is specific to the Samsung architecture, with each SoC
26 registering the necessary information for the core gpio configuration
30 driver or machine to change gpio configuration.
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| H A D | overview.rst | 6 ------------
15 - S3C64XX: S3C6400 and S3C6410
16 - S5PC110 / S5PV210
19 Configuration chapter
20 -------------
26 - S5PC110 specific default configuration
28 - S5PV210 specific default configuration
32 ------
35 several platform directories and then the machine specific directories
38 plat-samsung provides the base for all the implementations, and is the
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| /linux/drivers/hwtracing/coresight/ |
| H A D | coresight-config.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* CoreSight Configuration Management - component and system wide configuration */
28 * system configuration - used by config data and devices.
33 /* flags defining device instance matching - used in config match desc data. */
37 * Limit number of presets in a configuration
40 * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
66 * @hw_info: optional hardware device type specific information. (ETM / CTI specific etc)
69 * @mask32: 32 bit mask when using 32 bit value to access device register - if mask type.
89 * Device feature descriptor - combination of registers and parameters to
90 * program a device to implement a specific complex function.
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | dvo_ns2501.c | 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
81 * configuration. It should be 0x32 whenever regC0 is 0x05 (hsync off)
97 * PLL configuration register. This is a pair of registers,
102 #define NS2501_REG1C 0x1c /* low-part of the second register */
103 #define NS2501_REG1D 0x1d /* high-part of the second register */
108 * 2^16/control-value. The low-byte comes first.
110 #define NS2501_REG10 0x10 /* low-byte vertical scaler */
111 #define NS2501_REG11 0x11 /* high-byte vertical scaler */
112 #define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */
113 #define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /linux/Documentation/PCI/ |
| H A D | acpi-info.rst | 1 .. SPDX-License-Identifier: GPL-2.0
39 If the OS is expected to manage a non-discoverable device described via
40 ACPI, that device will have a specific _HID/_CID that tells the OS what
50 These are all device-specific, non-architected things, so the only way a
52 the device-specific details. The host bridge registers also include ECAM
66 bridge registers (including ECAM space) in PNP0C02 catch-all devices [6].
67 With the exception of ECAM, the bridge register space is device-specific
78 PNP0C02 "motherboard" devices are basically a catch-all. There's no
84 The PCIe spec requires the Enhanced Configuration Access Method (ECAM)
87 and converts memory accesses into PCI configuration accesses. The spec
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| /linux/drivers/net/ethernet/microchip/vcap/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Microchip VCAP API configuration
9 bool "VCAP (Versatile Content-Aware Processor) library"
15 - Programmable key fields
16 - Programmable action fields
17 - A counter (which may be only one bit wide)
21 - A number of lookups
22 - A keyset configuration per port per lookup
27 - Creating and deleting rules
28 - Updating and getting rules
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| /linux/drivers/rapidio/switches/ |
| H A D | idt_gen2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
188 * Switch domain configuration operates only at global level in idtg2_set_domain()
202 * Switch domain configuration operates only at global level in idtg2_get_domain()
219 * This routine performs device-specific initialization only. in idtg2_em_init()
220 * All standard EM configuration should be performed at upper level. in idtg2_em_init()
223 pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); in idtg2_em_init()
225 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */ in idtg2_em_init()
237 /* Use Port-Writes for LT layer error reporting. in idtg2_em_init()
238 * Enable per-port reset in idtg2_em_init()
251 /* Configure reporting of implementation specific errors/events */ in idtg2_em_init()
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| /linux/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| H A D | config.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2019, 2023-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
20 * @valid: valid antenna configuration
27 * struct iwl_calib_ctrl - Calibration control struct.
28 * Sent as part of the phy configuration command.
65 * struct iwl_phy_specific_cfg - specific PHY filter configuration
67 * Sent as part of the phy configuration command (v3) to configure specific FW
79 * struct iwl_phy_cfg_cmd_v1 - Phy configuration command
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| /linux/Documentation/userspace-api/media/mediactl/ |
| H A D | request-api.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
4 .. _media-request-api:
12 the same pipeline to reconfigure and collaborate closely on a per-frame basis.
14 to specific frames (aka 'per-frame controls') in order to be used efficiently.
16 While the initial use-case was V4L2, it can be extended to other subsystems
20 it is, it is terribly inefficient: user-space would have to flush all activity
22 be processed with that configuration, and wait until they are all available for
26 The Request API allows a specific configuration of the pipeline (media
27 controller topology + configuration for each media entity) to be associated with
28 specific buffers. This allows user-space to schedule several tasks ("requests")
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| /linux/Documentation/networking/devlink/ |
| H A D | devlink-dpipe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
32 greatly to the hardware implementation. The configuration API is the same,
34 Level Path Compression trie (LPC-trie) in hardware.
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
46 modeled as a graph of match/action tables. Each table represents a specific
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
53 standard configuration tools.
75 the actual content of a specific table.
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| /linux/Documentation/admin-guide/pm/ |
| H A D | suspend-flows.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 At least one global system-wide transition needs to be carried out for the
14 :doc:`sleep states <sleep-states>`. Hibernation requires more than one
16 referred to as *system-wide suspend* (or simply *system suspend*) states, need
27 significant differences between the :ref:`suspend-to-idle <s2idle>` code flows
28 and the code flows related to the :ref:`suspend-to-RAM <s2ram>` and
31 The :ref:`suspend-to-RAM <s2ram>` and :ref:`standby <standby>` sleep states
33 boils down to the platform-specific actions carried out by the suspend and
37 *platform-dependent suspend* states in what follows.
42 Suspend-to-idle Suspend Code Flow
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| /linux/Documentation/driver-api/xilinx/ |
| H A D | eemi.rst | 6 -------------------------------------
7 The zynqmp-firmware node describes the interface to platform firmware.
13 ----------------------------------------------
23 ------
24 IOCTL API is for device control and configuration. It is not a system
26 any device specific configuration. IOCTL definitions can be platform
27 specific. This API also manage shared device configuration.
30 - IOCTL_SET_PLL_FRAC_MODE 8
31 - IOCTL_GET_PLL_FRAC_MODE 9
32 - IOCTL_SET_PLL_FRAC_DATA 10
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| /linux/Documentation/arch/arm64/ |
| H A D | gcs.rst | 14 -----------
22 PE which is writeable only through specific GCS operations. This
29 via specific GCS instructions.
47 * GCS specific errors (those reported with EC 0x2d) will be reported as
53 regardless of the GCS configuration for the thread.
62 -------------------------------------------------
78 * Any unknown flags will cause PR_SET_SHADOW_STACK_STATUS to return -EINVAL.
93 * New threads inherit the GCS configuration of the thread that created them.
97 * The current GCS configuration for a thread may be read with the
114 ----------------------------------------
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| /linux/Documentation/driver-api/usb/ |
| H A D | writing_musb_glue_layer.rst | 15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
36 Devices also provide an overview of the Linux kernel MUSB configuration,
37 albeit focused on some specific devices provided by these companies.
46 ------------------------
47 | | <------- drivers/usb/gadget
48 | Linux USB Core Stack | <------- drivers/usb/host
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