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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap2430-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2430 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <2>;
31 #clock-cells = <0>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
[all …]
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
[all …]
H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP2420 clock data
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
[all …]
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
[all …]
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments mux clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
14 signals or parents, one of which can be selected as output. This clock does
24 register value selected parent clock
29 Some clock controller IPs do not allow a value of zero to be programmed
[all …]
H A Dmux.txt1 Binding for TI mux clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped multiplexer with multiple input clock signals or
5 parents, one of which can be selected as output. This clock does not
15 register value selected parent clock
20 Some clock controller IPs do not allow a value of zero to be programmed
22 "index-starts-at-one" modified the scheme as follows:
24 register value selected clock parent
29 The binding must provide the register to control the mux. Optionally
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
H A Dcomposite.txt1 Binding for TI composite clock.
3 This binding uses the common clock binding[1]. It assumes a
4 register-mapped composite clock with multiple different sub-types;
6 a multiplexer clock with multiple input clock signals or parents, one
9 an adjustable clock rate divider, this behaves exactly as [3]
12 clock, this behaves exactly as [4]
15 merged to this clock. The component clocks shall be of one of the
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
[all …]
H A Dti,composite-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments composite clock
10 - Tero Kristo <kristo@kernel.org>
13 *Deprecated design pattern: one node per clock*
15 This binding assumes a register-mapped composite clock with multiple
16 different sub-types:
18 a multiplexer clock with multiple input clock signals or parents, one
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 /* Fixed rate clock. */
88 /* Linked clock. */
101 /* Complex clock fo ARM cores. */
138 /* Full composite clock. */
142 .clk.composite = &(struct rk_clk_composite_def) { \
157 /* Composite clock without mux (divider only). */
161 .clk.composite = &(struct rk_clk_composite_def) { \
174 /* Complex clock without divider (multiplexer only). */
[all …]
H A Drk_cru.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 * RockChip Clock and Reset Unit
64 { -1, 0 }
67 #define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg))
68 #define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
119 if (id > sc->reset_num) in rk_cru_reset_assert()
122 reg = sc->reset_offset + id / 16 * 4; in rk_cru_reset_assert()
125 mtx_lock(&sc->mtx); in rk_cru_reset_assert()
130 mtx_unlock(&sc->mtx); in rk_cru_reset_assert()
[all …]
/freebsd/sys/arm64/freescale/imx/
H A Dimx_ccm.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
68 struct imx_clk_mux_def *mux; member
70 struct imx_clk_composite_def *composite; member
77 /* Linked clock. */
90 /* Complex clock without divider (multiplexer only). */
91 #define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \ macro
94 .clk.mux = &(struct imx_clk_mux_def) { \
107 /* Fixed frequency clock */
134 /* Clock gate */
[all …]
H A Dimx8mp_ccm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
73 * Table 5-1 of "i.MX 8M Plus Applications Processor Reference Manual" provides
74 * the Clock Root Table.
359 MUX(IMX8MP_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x00, 0, 2),
360 MUX(IMX8MP_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x14, 0, 2),
361 MUX(IMX8MP_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x28, 0, 2),
362 MUX(IMX8MP_DRAM_PLL_REF_SEL, "dram_pll_ref_sel", pll_ref_p, 0, 0x50, 0, 2),
363 MUX(IMX8MP_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x64, 0, 2),
364 MUX(IMX8MP_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x74, 0, 2),
[all …]
H A Dimx8mq_ccm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
136 MUX(IMX8MQ_ARM_PLL_REF_SEL, "arm_pll_ref_sel", pll_ref_p, 0, 0x28, 16, 2),
137 MUX(IMX8MQ_GPU_PLL_REF_SEL, "gpu_pll_ref_sel", pll_ref_p, 0, 0x18, 16, 2),
138 MUX(IMX8MQ_VPU_PLL_REF_SEL, "vpu_pll_ref_sel", pll_ref_p, 0, 0x20, 16, 2),
139 MUX(IMX8MQ_AUDIO_PLL1_REF_SEL, "audio_pll1_ref_sel", pll_ref_p, 0, 0x0, 16, 2),
140 MUX(IMX8MQ_AUDIO_PLL2_REF_SEL, "audio_pll2_ref_sel", pll_ref_p, 0, 0x8, 16, 2),
141 MUX(IMX8MQ_VIDEO_PLL1_REF_SEL, "video_pll1_ref_sel", pll_ref_p, 0, 0x10, 16, 2),
142 MUX(IMX8MQ_SYS3_PLL1_REF_SEL, "sys3_pll1_ref_sel", pll_ref_p, 0, 0x48, 0, 2),
143 MUX(IMX8MQ_DRAM_PLL1_REF_SEL, "dram_pll1_ref_sel", pll_ref_p, 0, 0x60, 0, 2),
[all …]
H A Dimx_ccm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * Clock Control Module driver for Freescale i.MX 8M SoC family.
64 return (bus_read_4(sc->mem_res, off)); in CCU_READ4()
71 bus_write_4(sc->mem_res, off, val); in CCU_WRITE4()
81 if (sc->mem_res != NULL) in imx_ccm_detach()
82 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); in imx_ccm_detach()
96 sc->dev = dev; in imx_ccm_attach()
101 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in imx_ccm_attach()
103 if (sc->mem_res == NULL) { in imx_ccm_attach()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Dctrl.txt5 described in [1]. Typically some clock nodes are also under control module.
9 See [2] for documentation about clock/clockdomain nodes.
11 [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
12 [2] Documentation/devicetree/bindings/clock/ti/*
15 - compatible: Must be one of:
16 "ti,am3-scm"
17 "ti,am4-scm"
18 "ti,dm814-scrm"
19 "ti,dm816-scrm"
20 "ti,omap2-sc
[all...]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-demux-pinctrl.txt1 Pinctrl-based I2C Bus DeMux
10 +-------------------------------+
12 | | +-----+ +-----+
13 | +------------+ | | dev | | dev |
14 | |I2C IP Core1|--\ | +-----+ +-----+
15 | +------------+ \-------+ | | |
16 | |Pinctrl|--|------+--------+
17 | +------------+ +-------+ |
18 | |I2C IP Core2|--/ |
19 | +------------+ |
[all …]
/freebsd/sys/arm/ti/clk/
H A Dti_mux_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
55 * Documentation/devicetree/bindings/clock/ti/mux.txt
76 { "ti,mux-clock", TI_MUX_CLOCK },
77 { "ti,composite-mux-clock", TI_COMPOSITE_MUX_CLOCK },
87 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in ti_mux_probe()
90 device_set_desc(dev, "TI Mux Clock"); in ti_mux_probe()
99 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk()
100 if (sc->clkdom == NULL) { in register_clk()
101 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gx-libretech-pc.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 /* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/sound/meson-aiu.h>
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 0>;
17 io-channel-names = "buttons";
18 keyup-threshold-microvolt = <1800000>;
[all …]
H A Dmeson-libretech-cottonwood.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/g12a-clkc.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/gpio/meson-g12a-gpio.h>
12 #include <dt-bindings/sound/meson-g12a-toacodec.h>
13 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
28 stdout-path = "serial0:115200n8";
31 dioo2133: audio-amplifier-0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6dl-prtvt7.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "imx6qdl-prti6q.dtsi"
9 #include <dt-bindings/display/sdtv-standards.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
23 backlight_lcd: backlight-lcd {
24 compatible = "pwm-backlight";
26 brightness-levels = <0 20 81 248 1000>;
[all …]
H A Dimx6qdl-vicut1.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 #include <dt-bindings/display/sdtv-standards.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/media/tvp5150.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
16 stdout-path = &uart4;
20 compatible = "pwm-backlight";
21 pinctrl-names = "default";
[all …]

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