Lines Matching +full:composite +full:- +full:mux +full:- +full:clock

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
35  * Clock Control Module driver for Freescale i.MX 8M SoC family.
64 	return (bus_read_4(sc->mem_res, off));  in CCU_READ4()
71 	bus_write_4(sc->mem_res, off, val);  in CCU_WRITE4()
81 	if (sc->mem_res != NULL)  in imx_ccm_detach()
82 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);  in imx_ccm_detach()
96 	sc->dev = dev;  in imx_ccm_attach()
101 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,  in imx_ccm_attach()
103 	if (sc->mem_res == NULL) {  in imx_ccm_attach()
109 	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);  in imx_ccm_attach()
111 	sc->clkdom = clkdom_create(dev);  in imx_ccm_attach()
112 	if (sc->clkdom == NULL)  in imx_ccm_attach()
115 	for (i = 0; i < sc->nclks; i++) {  in imx_ccm_attach()
116 		switch (sc->clks[i].type) {  in imx_ccm_attach()
120 			clknode_link_register(sc->clkdom,  in imx_ccm_attach()
121 			    sc->clks[i].clk.link);  in imx_ccm_attach()
124 			clknode_fixed_register(sc->clkdom,  in imx_ccm_attach()
125 			    sc->clks[i].clk.fixed);  in imx_ccm_attach()
128 			imx_clk_mux_register(sc->clkdom, sc->clks[i].clk.mux);  in imx_ccm_attach()
131 			imx_clk_gate_register(sc->clkdom, sc->clks[i].clk.gate);  in imx_ccm_attach()
134 			imx_clk_composite_register(sc->clkdom, sc->clks[i].clk.composite);  in imx_ccm_attach()
137 			imx_clk_sscg_pll_register(sc->clkdom, sc->clks[i].clk.sscg_pll);  in imx_ccm_attach()
140 			imx_clk_frac_pll_register(sc->clkdom, sc->clks[i].clk.frac_pll);  in imx_ccm_attach()
143 			clknode_div_register(sc->clkdom, sc->clks[i].clk.div);  in imx_ccm_attach()
146 			device_printf(dev, "Unknown clock type %d\n", sc->clks[i].type);  in imx_ccm_attach()
151 	if (clkdom_finit(sc->clkdom) != 0)  in imx_ccm_attach()
155 		clkdom_dump(sc->clkdom);  in imx_ccm_attach()
213 	mtx_lock(&sc->mtx);  in imx_ccm_device_lock()
222 	mtx_unlock(&sc->mtx);  in imx_ccm_device_unlock()