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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
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H A Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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H A Damlogic,meson-g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,meson-g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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H A Damlogic,g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <neil.armstrong@linaro.org>
16 - amlogic,g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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H A Dcalxeda-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
24 '#phy-cells':
36 - compatible
37 - reg
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H A Drockchip,rk3588-hdptx-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
10 - Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
15 - rockchip,rk3588-hdptx-phy
22 - description: Reference clock
23 - description: APB clock
25 clock-names:
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H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
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H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
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H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USBDP Combo PHY with Samsung IP block
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3588-usbdp-phy
21 "#phy-cells":
23 Cell allows setting the type of the PHY. Possible values are:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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H A Dnxp,ptn36502.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP PTN36502 Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver
10 - Luca Weiss <luca.weiss@fairphone.com>
15 - nxp,ptn36502
20 vdd18-supply:
23 orientation-switch: true
24 retimer-switch: true
31 description: Super Speed (SS) Output endpoint to the Type-C connector
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/
H A Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-range
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H A Dbcm958742k.dts4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 /dts-v1/;
35 #include "bcm958742-base.dtsi"
39 model = "Stingray Combo SVK (BCM958742K)";
43 enet-phy-lane-swap;
47 mmc-ddr-1_8v;
59 pinctrl-0 = <&spi0_pins>;
60 pinctrl-names = "default";
61 cs-gpios = <&gpio_hsls 34 0>;
65 compatible = "jedec,spi-nor";
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/freebsd/share/man/man4/
H A Dxl.415 .\" 4. Neither the name of the author nor the names of any co-contributors
41 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
57 and "tornado" bus-master Etherlink XL chips.
59 The Etherlink XL chips support built-in 10baseT, 10base2 and 10base5
60 transceivers as well as an MII bus for externally attached PHY
63 NS 83840A 10/100 PHY for 10/100 Mbps support in full or half-duplex.
64 The 3c905B adapters have built-in autonegotiation logic mapped onto
67 adapters such as the 3c905-TX and 3c905B-TX are capable of 10 or
75 .Bl -tag -width xxxxxxxxxxxxxxxxxxxx
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/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Decx-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h618-longanpi-3h.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h618-longan-module-3h.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/leds/common.h>
16 compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618";
24 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
30 led-0 {
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCA807x Ethernet PHY
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
14 Qualcomm QCA8072/5 Ethernet PHY is PHY package of 2 or 5
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
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/freebsd/sys/contrib/device-tree/Bindings/display/sprd/
H A Dsprd,display-subsystem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kevin Tang <kevin.tang@unisoc.com>
23 dpu0 and dpu1 both binding to DSI for dual mipi-dsi display;
26 +-----------------------------------------+
28 | +---------+ |
29 +----+ | +----+ +---------+ |DPHY/CPHY| | +------+
30 | +----->+dpu0+--->+MIPI|DSI +--->+Combo +----->+Panel0|
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "rk3588-friendlyelec-cm3588.dtsi"
19 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
21 adc_key_recovery: adc-key-recovery {
22 compatible = "adc-keys";
[all …]
H A Drk3566-box-demo.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/soc/rockchip,vop2.h>
18 compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566";
28 stdout-path = "serial2:1500000n8";
31 gmac1_clkin: external-gmac1-clock {
32 compatible = "fixed-clock";
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-overo-base.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
17 led-controller {
18 compatible = "pwm-leds";
20 led-1 {
23 max-brightness = <127>;
24 linux,default-trigger = "mmc0";
29 compatible = "ti,omap-twl4030";
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
39 regulator-min-microvolt = <5000000>;
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/freebsd/sys/dev/xl/
H A Dif_xl.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
[all …]
/freebsd/sys/arm64/rockchip/
H A Drk3568_combphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dev/phy/phy.h>
49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
57 {"rockchip,rk3568-naneng-combphy", 1},
163 /* PHY class and methods */
174 switch (sc->mode) { in rk3568_combphy_enable()
179 bus_write_4(sc->mem, PHYREG7, in rk3568_combphy_enable()
183 bus_write_4(sc->mem, PHYREG15, in rk3568_combphy_enable()
184 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
114 #define VGE_PHYSTS0 0x6E /* PHY status register */
115 #define VGE_PHYSTS1 0x6F /* PHY status register */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
274 #define VGE_ISR_TXOK 0x00000008 /* combo results for next 4 bits */
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/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35 gpio-keys {
36 compatible = "gpio-keys-polled";
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