Lines Matching +full:combo +full:- +full:phy

1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
18  * 4. Neither the name of the author nor the names of any co-contributors
37  * Definitions for the built-in copper PHY can be found in vgphy.h.
41  * using 32-bit I/O cycles, but some of them are less than 32 bits
114 #define VGE_PHYSTS0		0x6E	/* PHY status register */
115 #define VGE_PHYSTS1		0x6F	/* PHY status register */
119 #define VGE_SSTIMER		0x74	/* single-shot timer */
233 #define VGE_CR3_INT_SWPEND		0x01 /* disable multi-level int bits */
274 #define VGE_ISR_TXOK		0x00000008 /* combo results for next 4 bits */
288 #define VGE_ISR_PHYINT		0x00080000 /* PHY interrupt */
312 #define VGE_IMR_TXOK		0x00000008 /* combo results for next 4 bits */
326 #define VGE_IMR_PHYINT		0x00080000 /* PHY interrupt */
386  * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
389  * - The behavior of the interrupt holdoff timer register at offset
393  * - The behavior the WOL pattern programming registers at offset
416 #define VGE_MIICFG_PHYADDR	0x1F	/* PHY address (internal PHY is 1) */
429 /* PHY status register */
433 #define VGE_PHYSTS_SPEED10	0x04	/* PHY in 10Mbps mode */
434 #define VGE_PHYSTS_SPEED1000	0x08	/* PHY in giga mode */
435 #define VGE_PHYSTS_FDX		0x10	/* PHY in full duplex mode */
456 #define VGE_CHIPCFG0_PACPI	0x01	/* pre-ACPI wakeup function */
460 #define VGE_CHIPCFG0_PHLED	0x30	/* phy LED select */
537 #define VGE_TXCFG_NONBLK	0x02	/* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR	0x0C	/* non-blocking threshold */
590 #define	VGE_MIB_CNT		(VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
650 #define VGE_DIAGCTL_PHYINT_ENB	0x01	/* Enable PHY interrupts */