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Searched +full:coherency +full:- +full:manager (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
99 functions of the driver includes re-configuring AC timing
135 the EMIF PM code must run from on-chip SRAM late in the suspend
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/linux/Documentation/gpu/
H A Ddrm-mm.rst6 frame buffers, textures, vertices and other graphics-related data. Given
11 The DRM core includes two memory managers, namely Translation Table Manager
12 (TTM) and Graphics Execution Manager (GEM). TTM was the first DRM memory
13 manager to be developed and tried to be a one-size-fits-them all
20 GEM started as an Intel-sponsored project in reaction to TTM's
22 providing a solution to every graphics memory-related problems, GEM
28 The Translation Table Manager (TTM)
31 .. kernel-doc:: drivers/gpu/drm/ttm/ttm_module.c
34 .. kernel-doc:: include/drm/ttm/ttm_caching.h
38 ---------------------------
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/linux/drivers/block/drbd/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 DRBD is a shared-nothing, synchronously replicated block device. It
21 clusters and in this context, is a "drop-in" replacement for shared
31 DRBD can also be used in dual-Primary mode (device writable on both
33 shared-nothing cluster. Needless to say, on top of dual-Primary
35 cache coherency.
37 For automatic failover you need a cluster manager (e.g. heartbeat).
38 See also: https://www.drbd.org/, http://www.linux-ha.org
/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 acts as directory-based coherency manager.
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
29 - compatible
34 - items:
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/linux/Documentation/admin-guide/device-mapper/
H A Dcache.rst8 dm-cache is a device mapper target written by Joe Thornber, Heinz
15 This device-mapper solution allows us to insert this caching at
17 a thin-provisioning pool. Caching solutions that are integrated more
20 The target reuses the metadata library used in the thin-provisioning
23 The decision as to what data to migrate and when is left to a plug-in
46 Sub-devices
47 -----------
52 1. An origin device - the big, slow one.
54 2. A cache device - the small, fast one.
56 3. A small metadata device - records which blocks are in the cache,
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/linux/arch/mips/kernel/
H A Dsetup.c28 #include <linux/dma-map-ops.h>
44 #include <asm/smp-ops.h>
45 #include <asm/mips-cps.h>
79 unsigned long mips_io_port_base = -1;
163 * 64-bits values if the kernel has been built in pure in init_initrd()
164 * 32-bit. We need also to switch from KSEG0 to XKPHYS in init_initrd()
215 unsigned long size = initrd_end - initrd_start; in finalize_initrd()
235 printk(KERN_CONT " - disabling initrd\n"); in finalize_initrd()
276 * for bootmem setup initially, rely on the end-of-kernel-code in bootmem_init()
284 __pa_symbol(&_end) - __pa_symbol(&_text)); in bootmem_init()
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/linux/include/uapi/drm/
H A Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
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H A Dpvr_drm.h1 /* SPDX-License-Identifier: (GPL-2.0-only WITH Linux-syscall-note) OR MIT */
22 * - All members must be type-aligned.
23 * - The overall struct must be padded to 64-bit alignment.
24 * - Explicit padding is almost always required. This takes the form of
25 * ``_padding_[x]`` members of sufficient size to pad to the next power-of-two
29 * - Unions may only appear as the last member of a struct.
30 * - Individual union members may grow in the future. The space between the
41 * struct drm_pvr_obj_array - Container used to pass arrays of objects
67 * DRM_PVR_OBJ_ARRAY() - Helper macro for filling &struct drm_pvr_obj_array.
81 * PVR_IOCTL() - Build a PowerVR IOCTL number
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/linux/tools/include/uapi/drm/
H A Di915_drm.h19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
135 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
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/linux/arch/mips/mm/
H A Dc-r4k.c22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
388 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
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/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
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