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Searched full:cmu_fsys (Results 1 – 13 of 13) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Daxis,artpec8-clock.yaml141 - description: CMU_FSYS SCAN0 clock (from CMU_CMU)
142 - description: CMU_FSYS SCAN1 clock (from CMU_CMU)
143 - description: CMU_FSYS BUS clock (from CMU_CMU)
144 - description: CMU_FSYS IP clock (from CMU_CMU)
197 # Clock controller node for CMU_FSYS
201 cmu_fsys: clock-controller@16c10000 {
H A Dsamsung,exynos7885-clock.yaml103 - description: CMU_FSYS bus clock (from CMU_TOP)
H A Dsamsung,exynos5433-clock.yaml39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7870.dtsi266 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC0_ACLK>,
278 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC1_ACLK>,
290 clocks = <&cmu_fsys CLK_GOUT_FSYS_MMC2_ACLK>,
302 clocks = <&cmu_fsys CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER>,
303 <&cmu_fsys CLK_GOUT_FSYS_MUX_USB_PLL>;
315 clocks = <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD>,
316 <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK>,
317 <&cmu_fsys CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL>;
334 cmu_fsys: clock-controller@13730000 { label
H A Dexynos5433-tm2-common.dtsi261 &cmu_fsys {
264 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
[all …]
H A Dexynos7885.dtsi244 cmu_fsys: clock-controller@13400000 { label
306 clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
307 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
/linux/Documentation/devicetree/bindings/pci/
H A Dsamsung,exynos-pcie.yaml104 clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
/linux/include/dt-bindings/clock/
H A Dexynos7885.h136 /* CMU_FSYS */
H A Daxis,artpec8-clk.h83 /* CMU_FSYS */
H A Dexynos5260-clk.h262 /* List Of Clocks For CMU_FSYS */
H A Dexynos5433.h508 /* CMU_FSYS */
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h101 *Registers for CMU_FSYS
H A Dclk-artpec8.c557 /* Register Offset definitions for CMU_FSYS (0x16c10000) */