Searched full:cmu_cmu (Results 1 – 5 of 5) sorted by relevance
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and21 derived from CMU_CMU.86 - description: CMU_BUS BUS clock (from CMU_CMU)87 - description: CMU_BUS DLP clock (from CMU_CMU)105 - description: CMU_CORE main clock (from CMU_CMU)106 - description: CMU_CORE DLP clock (from CMU_CMU)124 - description: CMU_CPUCL switch clock (from CMU_CMU)141 - description: CMU_FSYS SCAN0 clock (from CMU_CMU)142 - description: CMU_FSYS SCAN1 clock (from CMU_CMU)143 - description: CMU_FSYS BUS clock (from CMU_CMU)[all …]
71 - description: IMEM TCU clock (from CMU_CMU)72 - description: IMEM bus clock (from CMU_CMU)73 - description: IMEM DMA clock (from CMU_CMU)91 - description: Shared0 PLL div4 clock (from CMU_CMU)92 - description: PERIC shared1 div36 clock (from CMU_CMU)93 - description: PERIC shared0 div3 TBU clock (from CMU_CMU)94 - description: PERIC shared0 div20 clock (from CMU_CMU)95 - description: PERIC shared1 div4 DMAclock (from CMU_CMU)115 - description: Shared0 PLL div6 clock (from CMU_CMU)116 - description: FSYS0 shared1 div4 clock (from CMU_CMU)[all …]
14 /* CMU_CMU */
23 /* Register Offset definitions for CMU_CMU (0x11c10000) */184 /* List of parent clocks for Muxes in CMU_CMU */
27 /* Register Offset definitions for CMU_CMU (0x12400000) */