cluster\-mode (full) in projects: linux

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Searched +full:cluster +full:- +full:mode (Results 1 – 25 of 263) sorted by relevance

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/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	other.json	3 … where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 7 …s running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX… 16 … running with power-delivery for license level 1. This includes high current AVX 256-bit instruct… 25 …running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). … 113 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 123 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 153 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 163 …et, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are con… 203 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 213 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", [all …]
/linux/drivers/remoteproc/
H A D	xlnx_r5_remoteproc.c	1 // SPDX-License-Identifier: GPL-2.0 7 #include <dt-bindings/power/xlnx-zynqmp-power.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/firmware/xlnx-zynqmp.h> 12 #include <linux/mailbox/zynqmp-ipi-message.h> 33 * settings for RPU cluster mode which 34 * reflects possible values of xlnx,cluster-mode dt-property 38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk / 43 struct mem_bank_data - Memory Bank description 48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a … 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 21 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 31 "Unit": "CPU-M-CF", [all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	extended.json	3 "Unit": "CPU-M-CF", 6 "BriefDescription": "L1D Read-only Exclusive Writes", 7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a … 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 21 …data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this … 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 31 "Unit": "CPU-M-CF", [all …]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	other.json	39 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 49 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 79 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 89 …her or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by … 129 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 159 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 169 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 249 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 259 …er or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by … 269 …her or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by … [all …]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	other.json	39 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 49 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 79 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 99 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 129 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 139 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 219 …t, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are con… 229 …er or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by … 269 … on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 303 … This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch misp… [all …]
/linux/drivers/md/
H A D	md-cluster.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 13 #include "md-bitmap.h" 14 #include "md-cluster.h" 27 void (bast)(void arg, int mode); /* blocking AST function pointer/ 29 int mode; member 47 / If cluster operations (such as adding a disk) must lock the 55 /* We should receive message after node joined cluster and 124 res->sync_locking_done = true; in sync_ast() 125 wake_up(&res->sync_locking); in sync_ast() 128 static int dlm_lock_sync(struct dlm_lock_resource *res, int mode) in dlm_lock_sync() argument [all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A D	ti,k3-r5f-rproc.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Suman Anna <s-anna@ti.com> 13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F 14 processor subsystems/clusters (R5FSS). The dual core cluster can be used 15 either in a LockStep mode providing safety/fault tolerance features or in a 16 Split mode providing two individual compute cores for doubling the compute 20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode [all …]
H A D	xlnx,zynqmp-r5fss.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ben Levinsky <ben.levinsky@amd.com> 11 - Tanmay Shah <tanmay.shah@amd.com> 14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for 15 real-time processing based on the Cortex-R5F processor core from ARM. 16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a 17 floating-point unit that implements the Arm VFPv3 instruction set. [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 108 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 111 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 114 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 117 …This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 120 … This event counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 123 …on": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in wr… 126 …on": "Level 2 cache write streaming mode. This event counts for each cycle where the core is in wr… 129 …"Level 1 data cache entering write streaming mode.This event counts for each entry into write-stre… 132 …"Level 1 data cache entering write streaming mode.This event counts for each entry into write-stre… [all …]
/linux/Documentation/driver-api/media/
H A D	v4l2-controls.rst	`1 .. SPDX-License-Identifier: GPL-2.0 7 ------------ 31 sub-device drivers. 35 ------------------------ 48 Basic usage for V4L2 and sub-device drivers 49 ------------------------------------------- 53 .. code-block:: c 55 #include <media/v4l2-ctrls.h> 57 1.1) Add the handler to your driver's top-level struct: 61 .. code-block:: c [all …]`
/linux/fs/fat/
H A D	fat.h	1 /* SPDX-License-Identifier: GPL-2.0 / 39 unsigned char errors; / On error: continue, panic, remount-ro / 47 utf8:1, / Use of UTF-8 character set (Default) / 64 MS-DOS file system in-core superblock data 67 unsigned short sec_per_clus; /* sectors/cluster / 69 unsigned int cluster_size; / cluster size / 76 unsigned long max_cluster; / maximum cluster number / 77 unsigned long root_cluster; / first cluster of the root directory / 82 unsigned int prev_free; / previously allocated cluster number / 83 unsigned int free_clusters; / -1 if undefined */ [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	cache.json	102 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 105 …-complex L2 cache, this event does not count. If the complex is configured without a per-complex L… 114 …ription": "L2 cache write streaming mode. This event counts for each cycle where the core is in wr… 117 …ription": "L2 cache write streaming mode. This event counts for each cycle where the core is in wr… 120 …n": "L1 data cache entering write streaming mode. This event counts for each entry into write stre… 123 …n": "L1 data cache entering write streaming mode. This event counts for each entry into write stre… 126 …on": "L1 data cache write streaming mode. This event counts for each cycle where the core is in wr… 129 …on": "L1 data cache write streaming mode. This event counts for each cycle where the core is in wr… 132 …ription": "L3 cache write streaming mode. This event counts for each cycle where the core is in wr… 135 …ription": "L3 cache write streaming mode. This event counts for each cycle where the core is in wr… [all …]
/linux/fs/dlm/
H A D	lockspace.c	1 // SPDX-License-Identifier: GPL-2.0-only 5 Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved. 6 Copyright (C) 2004-2011 Red Hat, Inc. All rights reserved. 43 return -EINVAL; in dlm_control_store() 53 ret = -EINVAL; in dlm_control_store() 61 int rc = kstrtoint(buf, 0, &ls->ls_uevent_result); in dlm_event_store() 65 set_bit(LSFL_UEVENT_WAIT, &ls->ls_flags); in dlm_event_store() 66 wake_up(&ls->ls_uevent_wait); in dlm_event_store() 72 return snprintf(buf, PAGE_SIZE, "%u\n", ls->ls_global_id); in dlm_id_show() 77 int rc = kstrtouint(buf, 0, &ls->ls_global_id); in dlm_id_store() [all …]
/linux/include/linux/
H A D	dlm.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 5 * Copyright (C) Sistina Software, Inc. 1997-2003 All rights reserved. 6 ** Copyright (C) 2004-2011 Red Hat, Inc. All rights reserved. 49 * cluster: cluster name, null terminated, up to DLM_LOCKSPACE_LEN (not 50 * including terminating null). Optional. When cluster is null, it 51 * is not used. When set, dlm_new_lockspace() returns -EBADR if cluster 52 * is not equal to the dlm cluster name. 60 * dlm_new_lockspace() should return -EEXIST if the lockspace exists. 79 * be used or not. 0: will be used, -EXXX will not be used. 80 * -EOPNOTSUPP: the dlm does not have recovery_callbacks enabled. [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	cache.json	111 … prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache", 114 …o prefetch. Counts any linefills from the prefetcher which cause an allocation into the L1 D-cache" 117 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 120 …-core L2 cache: This event does not count. +//0 If the core is configured without a per-core L2 ca… 123 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 126 …her they allocate. If either the core is configured without a per-core L2 or the cluster is config… 129 "PublicDescription": "L1D entering write stream mode", 132 "BriefDescription": "L1D entering write stream mode" 135 "PublicDescription": "L1D is in write stream mode", 138 "BriefDescription": "L1D is in write stream mode" [all …]
/linux/fs/exfat/
H A D	exfat_fs.h	1 /* SPDX-License-Identifier: GPL-2.0-or-later / 3 Copyright (C) 2012-2013 Samsung Electronics Co., Ltd. 50 (ES_IDX_FIRST_FILENAME + EXFAT_FILENAME_ENTRY_NUM(name_len) - 1) 76 #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character / 80 #define EXFAT_HINT_NONE -1 84 helpers for cluster size to byte conversion. 86 #define EXFAT_CLU_TO_B(b, sbi) ((b) << (sbi)->cluster_size_bits) 87 #define EXFAT_B_TO_CLU(b, sbi) ((b) >> (sbi)->cluster_size_bits) 89 (((b - 1) >> (sbi)->cluster_size_bits) + 1) 90 #define EXFAT_CLU_OFFSET(off, sbi) ((off) & ((sbi)->cluster_size - 1)) [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	cache.json	3 …the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might in… 42 … and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated re… 49 "BriefDescription": "Counts all the load micro-ops retired", 53 "PublicDescription": "This event counts the number of load micro-ops retired.", 58 "BriefDescription": "Counts all the store micro-ops retired", 62 "PublicDescription": "This event counts the number of store micro-ops retired.", 73 …"PublicDescription": "This event counts the number of load micro-ops retired that got data from an… 78 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache", 82 …"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data … 87 …"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2 (Precise Event… [all …]
/linux/arch/arm/mach-exynos/
H A D	common.h	1 /* SPDX-License-Identifier: GPL-2.0 / 12 #include <linux/platform_data/cpuidle-exynos.h> 113 / CPU BOOT mode flag for Exynos3250 SoC bootloader / 116 Magic values for bootloader indicating chosen low power mode. 117 * See also Documentation/arch/arm/samsung/bootloader-interface.rst 123 void exynos_set_boot_flag(unsigned int cpu, unsigned int mode); 124 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode); 140 extern void exynos_cluster_power_down(int cluster); 141 extern void exynos_cluster_power_up(int cluster); 142 extern int exynos_cluster_power_state(int cluster);
H A D	platsmp.c	1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5 // Cloned from linux/arch/arm/mach-vexpress/platsmp.c 17 #include <linux/soc/samsung/exynos-regs-pmu.h> 29 /* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX / 30 volatile int exynos_pen_release = -1; 70 having been woken up - this shouldn't happen in platform_do_lowpower() 72 * Just note it happening - when we're woken, we can report in platform_do_lowpower() 81 * exynos_cpu_power_down() - power down the specified cpu 109 * exynos_cpu_power_up() - power up the specified cpu [all …]
/linux/drivers/phy/marvell/
H A D	phy-armada375-usb2.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 * USB cluster support for Armada 375 platform. 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 10 * USB3 controller. The USB cluster control register allows to manage 14 #include <dt-bindings/phy/phy.h> 38 return -ENODEV; in armada375_usb_phy_init() 40 reg = readl(cluster_phy->reg); in armada375_usb_phy_init() 41 if (cluster_phy->use_usb3) in armada375_usb_phy_init() 45 writel(reg, cluster_phy->reg); in armada375_usb_phy_init() 69 return ERR_PTR(-ENODEV); in armada375_usb_phy_xlate() [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	other.json	3 "BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. the event also counts for Machine Ordering count.", 7 "PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists. the event also counts for Machine Ordering count.", 48 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster [all...]
/linux/tools/perf/Documentation/
H A D	perf-stat.txt	`1 perf-stat(1) 5 ---- 6 perf-stat - Run a command and gather performance counter statistics 9 -------- 11 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] <command> 12 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] \-- <command> [<options>] 13 'perf stat' [-e <EVENT> \| --event=EVENT] [-a] record [-o file] \-- <command> [<options>] 14 'perf stat' report [-i file] 17 ----------- 23 ------- [all …]`
/linux/include/media/drv-intf/
H A D	cx2341x.h	`1 /* SPDX-License-Identifier: GPL-2.0-or-later / 10 #include <media/v4l2-ctrls.h> 121 / audio cluster / 133 / video gop cluster / 139 / stream type cluster / 148 / video mute cluster / 154 / video filter mode cluster / 161 / video filter type cluster / 167 / video filter cluster / 173 / video median cluster */ [all …]`
/linux/arch/x86/kvm/svm/
H A D	avic.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Kernel-based Virtual Machine driver for Linux 19 #include <linux/amd-iommu.h> 60 static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_ID_MASK) == -1u); 81 struct list_head node; /* Used by SVM for per-vcpu ir_list / 87 struct vmcb vmcb = svm->vmcb01.ptr; in avic_activate_vmcb() 89 vmcb->control.int_ctl &= ~(AVIC_ENABLE_MASK \| X2APIC_MODE_MASK); in avic_activate_vmcb() 90 vmcb->control.avic_physical_id &= ~AVIC_PHYSICAL_MAX_INDEX_MASK; in avic_activate_vmcb() 92 vmcb->control.int_ctl \|= AVIC_ENABLE_MASK; in avic_activate_vmcb() 95 * Note: KVM supports hybrid-AVIC mode, where KVM emulates x2APIC MSR in avic_activate_vmcb() [all …]

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