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/linux/arch/arm/boot/dts/ti/omap/
H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
[all …]
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
[all …]
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
[all …]
H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34XX/OMAP36XX clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
16 clock@a14 {
19 #clock-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
H A Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
H A Dkeystone-k2hk-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking SoC clock nodes
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
15 reg-names = "control";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
23 reg-names = "control", "multiplier", "post-divider";
[all …]
H A Dkeystone-k2l-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 lamarr SoC clock nodes
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
15 reg-names = "control";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
23 reg-names = "control", "multiplier", "post-divider";
[all …]
H A Dkeystone-k2e-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,main-pll-clock";
14 reg-names = "control", "multiplier", "post-divider";
18 #clock-cells = <0>;
19 compatible = "ti,keystone,pll-clock";
21 clock-output-names = "papllclk";
23 reg-names = "control";
27 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-clock.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/dma/fsl-edma.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
12 audio_ipg_clk: clock-audio-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <120000000>;
[all …]
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
H A Dimx8-ss-mipi1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi1: interrupt-controller@57220000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
H A Dimx8-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
H A Dimx8qm-ss-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 /delete-node/ &acm;
8 /delete-node/ &sai4;
9 /delete-node/ &sai5;
10 /delete-node/ &sai4_lpcg;
11 /delete-node/ &sai5_lpcg;
37 power-domains = <&pd IMX_SC_R_ASRC_0>;
43 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>;
44 clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk";
67 power-domains = <&pd IMX_SC_R_ASRC_1>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-usb-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 USB Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 The additional ID argument passed to the clock shall refer to
20 the index of the output.
[all …]
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
H A Dbrcm,kona-ccu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,kona-ccu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family clock control units (CCU)
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
15 Broadcom "Kona" style clock control unit (CCU) is a clock provider that
16 manages a set of clock signals.
[all …]
H A Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
[all …]
H A Dnvidia,tegra124-dfll.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
17 encoder clock source and contains additional TV TCON and DSI gates.
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dallwinner,sun8i-a23-prcm.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun8i-a23-prcm
30 - fixed-factor-clock
31 - allwinner,sun8i-a23-apb0-clk
32 - allwinner,sun8i-a23-apb0-gates-clk
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-clks.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
15 ccpclk_375mhz: clock-375000000 {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
[all …]

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