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/linux/arch/arm64/boot/dts/renesas/
H A Dsalvator-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for common parts of Salvator-X board variants
5 * Copyright (C) 2015-2016 Renesas Electronics Corp.
9 * SSI-AK4613
13 * amixer set "DVC Out" 100%
18 * amixer set "DVC Out Mute" on
23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
25 * amixer set "DVC Out Ramp" on
27 * amixer set "DVC Out" 80% // Volume Down
[all …]
H A Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
10 * > amixer set "DVC Out" 1%
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
18 model = "Renesas R-Car Gen3 ULCB board";
37 stdout-path = "serial0:115200n8";
40 audio_clkout: audio-clkout {
43 * but needed to avoid cs2000/rcar_sound probe dead-lock
45 compatible = "fixed-clock";
[all …]
H A Dhihope-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/gpio/gpio.h>
30 stdout-path = "serial0:115200n8";
33 hdmi0-out {
34 compatible = "hdmi-connector";
39 remote-endpoint = <&rcar_dw_hdmi0_out>;
45 compatible = "gpio-leds";
64 reg_1p8v: regulator-1p8v {
65 compatible = "regulator-fixed";
66 regulator-name = "fixed-1.8V";
[all …]
/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7791-koelsch.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
35 * amixer set "DVC Out" 100% // Volume Up
[all …]
H A Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
[all …]
H A Dr8a7793-gose.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
9 * SSI-AK4643
18 * amixer set "DVC Out" 100%
23 * amixer set "DVC Out Mute" on
28 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
29 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
30 * amixer set "DVC Out Ramp" on
32 * amixer set "DVC Out" 80% // Volume Down
33 * amixer set "DVC Out" 100% // Volume Up
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_clock_utils.c1 // SPDX-License-Identifier: MIT
61 * Note that on gen11+, the clock frequency may be reconfigured. in gen11_read_clock_frequency()
64 * First figure out the reference frequency. There are 2 ways in gen11_read_clock_frequency()
65 * we can compute the frequency, either through the in gen11_read_clock_frequency()
77 * Now figure out how the command stream's timestamp in gen11_read_clock_frequency()
78 * register increments from this frequency (it might in gen11_read_clock_frequency()
79 * increment only every few clock cycle). in gen11_read_clock_frequency()
81 freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); in gen11_read_clock_frequency()
95 freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; in gen9_read_clock_frequency()
98 * Now figure out how the command stream's timestamp in gen9_read_clock_frequency()
[all …]
/linux/Documentation/devicetree/bindings/net/can/
H A Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
[all …]
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - const: renesas,r9a06g032-sja1000 # RZ/N1D
20 - const: renesas,rzn1-sja1000 # RZ/N1
[all …]
/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
[all …]
/linux/Documentation/timers/
H A Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
7 drivers/clocksource in the kernel tree, but the code may be spread out
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
19 - if:
24 - ethernet-phy-id004d.d0c0
33 - description:
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
/linux/sound/aoa/soundbus/i2sbus/
H A Dinterface.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
70 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_clock.c1 // SPDX-License-Identifier: GPL-2.0-only
41 static int measure_clock(struct adf_accel_dev *accel_dev, u32 *frequency) in measure_clock() argument
58 delta_us = timespec_to_us(&ts2) - timespec_to_us(&ts1); in measure_clock()
59 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
62 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
63 return -ETIMEDOUT; in measure_clock()
74 return -EIO; in measure_clock()
77 delta_us = timespec_to_us(&ts4) - timespec_to_us(&ts3); in measure_clock()
78 } while (delta_us > MEASURE_CLOCK_DELTA_THRESHOLD_US && --tries); in measure_clock()
81 dev_err(&GET_DEV(accel_dev), "Excessive clock measure delay\n"); in measure_clock()
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
16 * clock frequency of the oscillator in combination with the TIMINCA
25 * PeriodWidth: Number of bits to store the clock period
27 * Period: The clock period for the oscillator
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
41 * value in order to quickly convert it into a nanosecond clock,
47 * +--------------+ +--------------+
49 * *--------------+ +--------------+
52 * +--------------+ +--------------+
[all …]
/linux/drivers/i2c/busses/
H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
28 #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
32 #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
54 #define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
58 #define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
65 /* PCLK frequency */
68 /* STANDARD MODE frequency */
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
71 /* FAST MODE frequency */
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include "dra74-ipu-dsp-common.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/ti-dra7-atl.h>
9 #include <dt-bindings/input/input.h>
13 stdout-path = &uart1;
17 compatible = "linux,extcon-usb-gpio";
18 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
22 compatible = "linux,extcon-usb-gpio";
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12a-sei510.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-g12a.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/meson-g12a-gpio.h>
12 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
19 compatible = "adc-keys";
20 io-channels = <&saradc 0>;
21 io-channel-names = "buttons";
[all …]
H A Dmeson-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
22 stdout-path = "serial0:115200n8";
30 adc-keys {
31 compatible = "adc-keys";
32 io-channels = <&saradc 2>;
33 io-channel-names = "buttons";
[all …]
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850-lcdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
11 model = "DA850/AM1808/OMAP-L138 LCDK";
12 compatible = "ti,da850-lcdk", "ti,da850";
20 stdout-path = "serial2:115200n8";
28 reserved-memory {
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
/linux/drivers/net/can/cc770/
H A Dcc770_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * in your board-specific code:
29 * interrupt-parent = <&mpic>;
30 * bosch,external-clock-frequency = <16000000>;
53 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the platform bus");
61 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg()
67 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg()
74 struct device_node *np = pdev->dev.of_node; in cc770_get_of_node_data()
76 of_property_read_u32(np, "bosch,external-clock-frequency", &clkext); in cc770_get_of_node_data()
77 priv->can.clock.freq = clkext; in cc770_get_of_node_data()
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos2200-g0s.dts1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Samsung Galaxy S22+ (g0s/SM-S906B) device tree source
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "Samsung Galaxy S22+ (SM-S906B)";
17 chassis-type = "handset";
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux/arch/powerpc/include/asm/
H A Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 * Clock Control Module
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
35 u32 cccr; /* CFM Clock Control Register */
[all …]

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