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/linux/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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/linux/drivers/clk/renesas/
H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
37 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
39 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
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H A Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
36 * Z Clock
38 * Traits of this clock:
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
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H A Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
56 #define CPG_PLLxCR0_NI8 GENMASK(27, 20) /* Integer mult. factor */
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/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
8 clock@a00 {
11 #clock-cells = <2>;
12 #address-cells = <1>;
13 #size-cells = <0>;
15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 {
17 #clock-cells = <0>;
18 compatible = "ti,composite-no-wait-gate-clock";
19 clock-output-names = "ssi_ssr_gate_fck_3430es2";
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H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
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H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
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H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
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H A Domap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,omap3-dpll-per-j-type-clock";
16 #clock-cells = <0>;
17 compatible = "ti,hsdiv-gate-clock";
19 ti,bit-shift = <0x1e>;
21 ti,set-rate-parent;
22 ti,set-bit-to-disable;
26 #clock-cells = <0>;
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H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
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H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
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/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
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/linux/drivers/clk/sunxi/
H A Dclk-a10-pll2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sun4i-a10-pll2.h>
22 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
26 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
30 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup()
44 struct clk_multiplier *mult; in sun4i_pll2_setup() local
62 prediv_clk = clk_register_divider(NULL, "pll2-prediv", in sun4i_pll2_setup()
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H A Dclk-sun4i-pll3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup()
24 struct clk_multiplier *mult; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
44 gate->reg = reg; in sun4i_a10_pll3_setup()
45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup()
46 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
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/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
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/linux/include/linux/
H A Dclocksource.h1 /* SPDX-License-Identifier: GPL-2.0 */
36 * struct clocksource - hardware abstraction for a free running counter
37 * Provides mostly state-free accessors to the underlying hardware.
43 * @mult: Cycle to nanosecond multiplier
46 * @maxadj: Maximum adjustment value to mult (~11%)
49 * @archdata: Optional arch-specific data
60 * 1-99: Unfit for real use
62 * 100-199: Base level usability.
64 * 200-299: Good.
66 * 300-399: Desired.
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/linux/drivers/clk/ti/
H A Dfixed-factor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Fixed Factor Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
17 #include "clock.h"
23 * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
24 * @node: device node for this clock
26 * Sets up a simple fixed factor clock based on device tree info.
33 u32 div, mult; in of_ti_fixed_factor_clk_setup() local
36 if (of_property_read_u32(node, "ti,clock-div", &div)) { in of_ti_fixed_factor_clk_setup()
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/linux/drivers/clk/mvebu/
H A Dorion.c1 // SPDX-License-Identifier: GPL-2.0
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include <linux/clk-provider.h>
60 int *mult, int *div) in mv88f5181_get_clk_ratio() argument
65 *mult = 1; in mv88f5181_get_clk_ratio()
68 *mult = 1; in mv88f5181_get_clk_ratio()
71 *mult = 0; in mv88f5181_get_clk_ratio()
89 CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
128 int *mult, int *div) in mv88f5182_get_clk_ratio() argument
133 *mult = 1; in mv88f5182_get_clk_ratio()
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/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpllcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DPLL + CORE_CLK composite clock functions
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
15 * XXX The DPLL and CORE clocks should be split into two separate clock
26 #include "clock.h"
30 #include "cm-regbits-24xx.h"
38 * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set
44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
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/linux/drivers/clk/davinci/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 * PLL clock driver for TI Davinci SoCs
7 * Based on arch/arm/mach-davinci/clock.c
8 * Copyright (C) 2006-2007 Texas Instruments.
9 * Copyright (C) 2008-2009 Deep Root Systems, LLC
12 #include <linux/clk-provider.h>
22 #include <linux/platform_data/clk-davinci-pll.h>
79 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
86 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
90 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
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/linux/kernel/time/
H A Dtimekeeping.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/sched/clock.h>
28 #include "tick-internal.h"
62 * struct tk_fast - NMI safe timekeeper
75 /* Suspend-time cycles value for halted fast timekeeper. */
92 * returns nanoseconds already so no conversion is required, hence mult=1
98 .clock = &dummy_clock, \
100 .mult = 1, \
130 * Multigrain timestamps require tracking the latest fine-grained timestamp
131 * that has been issued, and never returning a coarse-grained timestamp that is
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H A Dclockevents.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains functions which manage clock event devices.
5 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
6 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
7 * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner
17 #include "tick-internal.h"
19 /* The registered clock event devices */
35 u64 clc = (u64) latch << evt->shift; in cev_delta2ns()
38 if (WARN_ON(!evt->mult)) in cev_delta2ns()
39 evt->mult = 1; in cev_delta2ns()
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/linux/drivers/net/can/rockchip/
H A Drockchip_canfd-timestamp.c1 // SPDX-License-Identifier: GPL-2.0
4 // Marc Kleine-Budde <kernel@pengutronix.de>
24 ns = timecounter_cyc2time(&priv->tc, timestamp); in rkcanfd_skb_set_timestamp()
26 hwtstamps->hwtstamp = ns_to_ktime(ns); in rkcanfd_skb_set_timestamp()
35 timecounter_read(&priv->tc); in rkcanfd_timestamp_work()
37 schedule_delayed_work(&priv->timestamp, priv->work_delay_jiffies); in rkcanfd_timestamp_work()
42 const struct can_bittiming *dbt = &priv->can.data_bittiming; in rkcanfd_timestamp_init()
43 const struct can_bittiming *bt = &priv->can.bittiming; in rkcanfd_timestamp_init()
44 struct cyclecounter *cc = &priv->cc; in rkcanfd_timestamp_init()
49 /* At the standard clock rate of 300Mhz on the rk3658, the 32 in rkcanfd_timestamp_init()
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/linux/drivers/ptp/
H A Dptp_mock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Mock-up PTP Hardware Clock driver for virtual network devices
7 * Create a PTP clock which offers PTP time manipulation operations
15 /* Clamp scaled_ppm between -2,097,152,000 and 2,097,152,000,
16 * and thus "adj" between -68,719,476 and 68,719,476
20 * (MULT >> SHIFT) needs to be 1. Pick SHIFT as 31 bits, which translates
21 * MULT(freq 0) into 0x80000000.
29 * 64-bit overflow during the multiplication with cc->mult, given the max "adj"
38 struct ptp_clock *clock; member
57 spin_lock(&phc->lock); in mock_phc_adjfine()
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/linux/Documentation/devicetree/bindings/clock/
H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - description:
17 If the frequency is fixed, the preferred name is 'clock-<freq>' with
19 pattern: "^clock-([0-9]+|[0-9a-z-]+)$"
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